| Pin # | SMARC Pin Name | Board Signal | CPU Pin | CPU Functions | Group | I/O Level | Comments |
|---|---|---|---|---|---|---|---|
| P1 | SMB_ALERT# | SOC_SMB_ALERT_N | R63 | SMB_ALERT_N | MANAGEMENT | PU 2k2 | SMBus Alert# (Interrupt) Signal |
| P2 | GND | PWR/GND | |||||
| P3 | CSI1_CK+ | CSI1_CLKP | M19 | MCSI_CLKP _0 | CSI1 | CSI1 differential clock input (point to point) | |
| P4 | CSI1_CK- | CSI1_CLKN | L19 | MCSI_CLKN _0 | CSI1 | CSI1 differential clock input (point to point) | |
| P5 | GBE1_SDP | NC | |||||
| P6 | GBE0_SDP | NC | |||||
| P7 | CSI1_RX0+ | CSI1_D0P | P17 | MCSI_DP_0 | CSI1 | CSI1 differential input (point to point) | |
| P8 | CSI1_RX0- | CSI1_D0N | M17 | MCSI_DN_0 | CSI1 | CSI1 differential input (point to point) | |
| P9 | GND | PWR/GND | |||||
| P10 | CSI1_RX1+ | CSI1_D1P | P21 | MCSI_DP_1 | CSI1 | CSI1 differential input (point to point) | |
| P11 | CSI1_RX1- | CSI1_D1N | R21 | MCSI_DN_1 | CSI1 | CSI1 differential input (point to point) | |
| P12 | GND | PWR/GND | |||||
| P13 | CSI1_RX2+ | CSI1_D2P | L17 | MCSI_DP_2 | CSI1 | CSI1 differential input (point to point) | |
| P14 | CSI1_RX2- | CSI1_D2N | J17 | MCSI_DN_2 | CSI1 | CSI1 differential input (point to point) | |
| P15 | GND | PWR/GND | |||||
| P16 | CSI1_RX3+ | CSI1_D3P | F17 | MCSI_DP_3 | CSI1 | ||
| P17 | CSI1_RX3- | CSI1_D3N | E17 | MCSI_DN_3 | CSI1 | ||
| P18 | GND | PWR/GND | |||||
| P19 | GBE0_MDI3- | ETH0_TX3N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P20 | GBE0_MDI3+ | ETH0_TX3P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P21 | GBE0_LINK100# | ETH0_LINK10/100_ | - | GBE0 | 3V3 | Link Speed Indication LED for GBE0 100Mbps | |
| P22 | GBE0_LINK1000# | ETH0_LINK1000_ | - | GBE0 | 3V3 | Link Speed Indication LED for GBE0 1000Mbps | |
| P23 | GBE0_MDI2- | ETH0_TX2N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P24 | GBE0_MDI2+ | ETH0_TX2P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P25 | GBE0_LINK_ACT# | ETH0_ACT_ | - | GBE0 | 3V3 | Link / Activity Indication LED Driven Low on Link (10, 100 or 1000 Mbps) Blinks on Activity | |
| P26 | GBE0_MDI1- | ETH0_TX1N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P27 | GBE0_MDI1+ | ETH0_TX1P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P28 | GBE0_CTREF | GBE0 | 0…3V3 | Center-Tap Reference Voltage for Carrier Board Ethernet Magnetic (if required by the Module GBE PHY) | |||
| P29 | GBE0_MDI0- | ETH0_TX0N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P30 | GBE0_MDI0+ | ETH0_TX0P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P31 | SPI0_CS1# | GP_SSP_0_FS1 | H52 | GP_SSP_0_FS1 | SPI | 1V8 | SPI Master Chip Select 1 |
| P32 | GND | PWR/GND | |||||
| P33 | SDIO_WP | SDIO_WP | AB55 | SDCARD_LVL_WP | SDIO | 3V3 PU10K | SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards. |
| P34 | SDIO_CMD | SDIO_CMD | AC52 | SDCARD_CMD | SDIO | 3V3 | SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode. |
| P35 | SDIO_CD# | SDIO_CD_N | AB54 | SDCARD_CD_N | SDIO | 3V3 | SDIO Card Detect. This signal indicates when a SDIO/MMC card is present. |
| P36 | SDIO_CK | SDIO_CK | AB58 | SDCARD_CLK | SDIO | 3V3 | SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. |
| P37 | SDIO_PWR_EN | SDIO_PWR_EN | C29 | GPIO_27 | SDIO | 3V3 | DIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device. |
| P38 | GND | PWR/GND | |||||
| P39 | SDIO_D0 | SDIO_D0 | AC49 | SDCARD_D0 | SDIO | 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P40 | SDIO_D1 | SDIO_D1 | AC48 | SDCARD_D1 | SDIO | 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P41 | SDIO_D2 | SDIO_D2 | AC51 | SDCARD_D2 | SDIO | 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P42 | SDIO_D3 | SDIO_D3 | AB51 | SDCARD_D3 | SDIO | 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P43 | SPI0_CS0# | GP_SSP_0_FS0 | P54 | GP_SSP_2_FS0 | SPI | 1V8 | SPI Master Chip Select 0 |
| P44 | SPI0_CK | GP_SSP_0_CLK | F54 | GP_SSP_0_CLK | SPI | 1V8 | SPI Clock |
| P45 | SPI0_DIN | GP_SSP_0_RXD | H54 | GP_SSP_0_RXD | SPI | 1V8 | SPI Master input / Slave output |
| P46 | SPI0_DO | GP_SSP_0_TXD | J52 | GP_SSP_0_TXD | SPI | 1V8 | SPI Master output / Slave input |
| P47 | GND | PWR/GND | |||||
| P48 | SATA_TX+ | SATA_TXP | Y3 | SATA_P0_TXP | SATA | Serial ATA Channel 0 Transmit Output Differential Pair | |
| P49 | SATA_TX- | SATA_TXN | Y2 | SATA_P0_TXN | SATA | Serial ATA Channel 0 Transmit Output Differential Pair | |
| P50 | GND | PWR/GND | |||||
| P51 | SATA_RX+ | SATA_RXP | T9 | SATA_P0_RXP | SATA | Serial ATA Channel 0 Receive Input Differential Pair | |
| P52 | SATA_RX- | SATA_RXN | T7 | SATA_P0_RXN | SATA | Serial ATA Channel 0 Receive Input Differential Pair | |
| P53 | GND | PWR/GND | |||||
| P54 | ESPI_CS0# / SPI1_CS0# / QSPI_CS0# | GP_SSP_2_FS0 | D61 | GP_SSP_2_FS0 | SPI1 Master Chip Select 0 | ||
| P55 | ESPI_CS1# / SPI1_CS1# / QSPI_CS1# | GP_SSP_2_FS1 | E56 | GP_SSP_2_FS1 | SPI1 Master Chip Select 1 | ||
| P56 | ESPI_CK / SPI1_CK / QSPI_CK | GP_SSP_2_CLK | F62 | GP_SSP_2_CLK | SPI1 Clock | ||
| P57 | ESPI_IO_1 / SPI1_DIN / QSPI_IO_1 | GP_SSP_2_RXD | C62 | GP_SSP_2_RXD | SPI1 Master input / Slave output | ||
| P58 | ESPI_IO_0 / SPI1_DO / QSPI_IO_0 | GP_SSP_2_TXD | E62 | GP_SSP_2_TXD | SPI1 Master output / Slave input | ||
| P59 | GND | PWR/GND | |||||
| P60 | USB0+ | USB0_DP | V12 | USB2_DP0 | USB0 | USB | USB Differential Data Pairs for Port 0 |
| P61 | USB0- | USB0_DN | V10 | USB2_DN0 | USB0 | USB | USB Differential Data Pairs for Port 0 |
| P62 | USB0_EN_OC# | USB0-2_EN_OC_ | B55 | USB_OC0_N | USB0 | PU 10k 3.3V | USB Over-Current Sense for Port 0 |
| P63 | USB0_VBUS_DET | ||||||
| P64 | USB0_OTG_ID | USB0 | Ground | ||||
| P65 | USB1+ | USB1_DP | V16 | USB2_DP1 | USB1 | USB | USB Differential Data Pairs for Port 1 |
| P66 | USB1- | USB1_DN | V15 | USB2_DN1 | USB1 | USB | USB Differential Data Pairs for Port 1 |
| P67 | USB1_EN_OC# | USB0-2_EN_OC_ | B55 | USB_OC0_N | USB1 | PU 10k 3.3V | USB Over-Current Sense for Port 1 |
| P68 | GND | PWR/GND | |||||
| P69 | USB2+ | USB2_DP | Y13 | USB2_DP2 | USB2 | USB | USB Differential Data Pairs for Port 2 |
| P70 | USB2- | USB2_DP | V13 | USB2_DN2 | USB2 | USB | USB Differential Data Pairs for Port 2 |
| P71 | USB2_EN_OC# | USB0-2_EN_OC_ | B55 | USB_OC0_N | USB2 | PU 10k 3.3V | USB Over-Current Sense for Port 2 |
| P72 | RSVD | RSVD | |||||
| P73 | RSVD | RSVD | |||||
| P74 | USB3_EN_OC# | USB3-5_EN_OC_ | C55 | USB_OC1_N | USB3 | PU 10k 3.3V | USB Over-Current Sense for Port 3 |
| P75 | PCIE_A_RST# | PCIe_RST_ | AG57 | PMU_PLTRST_N | PCIe0 | 3V3 | PCIe Port A reset output |
| P76 | USB4_EN_OC# | USB20_EN_OC_ | C55 | USB_OC1_N | USB4 | PU 10k 3.3V | USB Over-Current Sense for Port 4 |
| P77 | PCIE_B_CKREQ# | PCIe1_CLKREQ_ | AH62 | PCIE_CLKREQ1_N | PCIe1 | PCIe Port B clock request | |
| P78 | PCIE_A_CKREQ# | PCIe0_CLKREQ_ | AK62 | PCIE_CLKREQ0_N | PCIe0 | PCIe Port A clock request | |
| P79 | GND | PWR/GND | |||||
| P80 | PCIE_C_REFCK+ | PCIe2_CLKP | A7 | PCIE_CLKOUT2P | PCIE20 | Differential PCIe Link C reference clock output | |
| P81 | PCIE_C_REFCK- | PCIe2_CLKP | B8 | PCIE_CLKOUT2N | PCIE20 | Differential PCIe Link C reference clock output | |
| P82 | GND | PWR/GND | |||||
| P83 | PCIE_A_REFCK+ | PCIe0_CLKP | C11 | PCIE_CLKOUT0P | PCIe0 | Differential PCIe Link A reference clock output | |
| P84 | PCIE_A_REFCK- | PCIe0_CLKN | B11 | PCIE_CLKOUT0N | PCIe0 | Differential PCIe Link A reference clock output | |
| P85 | GND | PWR/GND | |||||
| P86 | PCIE_A_RX+ | PCIe0_RXP | P7 | PCIE_P0_RXP | PCIE30 | Differential PCIe link A receive data pair | |
| P87 | PCIE_A_RX- | PCIe0_RXN | P6 | PCIE_P0_RXN | PCIE30 | Differential PCIe link A receive data pair | |
| P88 | GND | PWR/GND | |||||
| P89 | PCIE_A_TX+ | PCIe0_TXP | V3 | PCIE_P0_TXP | PCIE30 | Differential PCIe link A transmit data pair | |
| P90 | PCIE_A_TX- | PCIe0_TXN | V2 | PCIE_P0_TXN | PCIE30 | Differential PCIe link A transmit data pair | |
| P91 | GND | PWR/GND | |||||
| P92 | HDMI_D2+ / DP1_LANE0+ | HDMI_D2+ | AK3 | DDI0_TXP_0 | HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P93 | HDMI_D2- / DP1_LANE0- | HDMI_D2- | AK2 | DDI0_TXN_0 | HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P94 | GND | PWR/GND | |||||
| P95 | HDMI_D1+ / DP1_LANE1+ | HDMI_D1+ | AM3 | DDI0_TXP_1 | HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P96 | HDMI_D1- / DP1_LANE1- | HDMI_D1- | AM2 | DDI0_TXN_1 | HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P97 | GND | PWR/GND | |||||
| P98 | HDMI_D0+ / DP1_LANE2+ | HDMI_D0+ | AH3 | DDI0_TXP_2 | HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P99 | HDMI_D0- / DP1_LANE2- | HDMI_D0- | AH2 | DDI0_TXN_2 | HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P100 | GND | PWR/GND | |||||
| P101 | HDMI_CK+ / DP1_LANE3+ | HDMI_CLK+ | AL2 | DDI0_TXP_3 | HDMI/DP | HDMI Port, Differential Pair Clock Lines | |
| P102 | HDMI_CK- / DP1_LANE3- | HDMI_CLK- | AL1 | DDI0_TXN_3 | HDMI/DP | HDMI Port, Differential Pair Clock Lines | |
| P103 | GND | PWR/GND | |||||
| P104 | HDMI_HPD / DP1_HPD | HDMI_HPD | C50 | GPIO_200 | HDMI/DP | PD 1M 1V8 | HDMI Hot Plug Active High Detection Signal that Serves as an Interrupt Request |
| P105 | HDMI_CTRL_CK / DP1_AUX+ | HDMI_SCL_DP1_AUX+ | B49 / AM16 | DDI0_DDC_SCL DDI0_AUXP |
HDMI/DP | PU 1V8 | I2C_CLK Line Dedicated to HDMI / DP1_AUX+ |
| P106 | HDMI_CTRL_DAT / DP1_AUX- | HDMI_SDA_DP1_AUX- | C49 / AM15 | DDI0_DDC_SSA DDI0_AUXN |
HDMI/DP | PU 1V8 | I2C_DAT Line Dedicated to HDMI / DP1_AUX- |
| P107 | DP1_AUX_SEL | DP1_AUX_SEL | С38 | GPIO_14 | DP1++_HDMI | 1V8 | Strapping Signal to Enable Either HDMI or DP Output |
| P108 | GPIO0 / CAM0_PWR# | SMARC_GPIO0 | A38 | GPIO_0 | GPIO | PU 470k 1V8 | GPIO Pin 0 Preferred Output |
| P109 | GPIO1 / CAM1_PWR# | SMARC_GPIO1 | B33 | GPIO_1 | GPIO | PU 470k 1V8 | GPIO Pin 1 Preferred Output |
| P110 | GPIO2 / CAM0_RST# | SMARC_GPIO2 | C39 | GPIO_2 | GPIO | PU 470k 1V8 | GPIO Pin 2 Preferred Output |
| P111 | GPIO3 / CAM1_RST# | SMARC_GPIO3 | B39 | GPIO_3 | GPIO | PU 470k 1V8 | GPIO Pin 3 Preferred Output |
| P112 | GPIO4 / HDA_RST# | SMARC_GPIO4 | B35 | GPIO_4 | GPIO | PU 470k 1V8 | GPIO Pin 4 Preferred Output |
| P113 | GPIO5 / PWM_OUT | SMARC_GPIO5 | A34 | GPIO_5 | GPIO | PU 470k 1V8 | GPIO Pin 5 Preferred Output |
| P114 | GPIO6 / TACHIN | SMARC_GPIO6 | B31 | GPIO_6 | GPIO | PU 470k 1V8 | GPIO Pin 6 Preferred Output |
| P115 | GPIO7 | SMARC_GPIO7 | H39 | GPIO_7 | GPIO | PU 470k 1V8 | GPIO Pin 7 Preferred Output |
| P116 | GPIO8 | SMARC_GPIO8 | B29 | GPIO_8 | GPIO | PU 470k 1V8 | GPIO Pin 8 Preferred Output |
| P117 | GPIO9 | SMARC_GPIO9 | A30 | GPIO_9 | GPIO | PU 470k 1V8 | GPIO Pin 9 Preferred Output |
| P118 | GPIO10 | SMARC_GPIO10 | L39 | GPIO_10 | GPIO | PU 470k 1V8 | GPIO Pin 10 Preferred Output |
| P119 | GPIO11 | SMARC_GPIO11 | C34 | GPIO_11 | GPIO | PU 470k 1V8 | GPIO Pin 11 Preferred Output |
| P120 | GND | PWR/GND | |||||
| P121 | I2C_PM_CK | SMARC_I2C_PM_CK | T62 | SMB_CLK | MANAGEMENT | PU 2.2K 1V8 | Power management I2C bus CLK |
| P122 | I2C_PM_DAT | SMARC_I2C_PM_DAT | T61 | SMB_DATA | MANAGEMENT | PU 2.2K 1V8 | Power management I2C bus DATA |
| P123 | BOOT_SEL0# | BOOT_SEL0_ | C27 | GPIO_25 | BOOT | PU 10K 1V8 | Input straps determine the Module boot device |
| P124 | BOOT_SEL1# | BOOT_SEL1_ | C25 | GPIO_24 | BOOT | PU 10K 1V8 | Input straps determine the Module boot device |
| P125 | BOOT_SEL2# | BOOT_SEL2_ | B25 | GPIO_23 | BOOT | PU 10K 1V8 | Input straps determine the Module boot device |
| P126 | RESET_OUT# | RESET_OUT_ | AG57 | PMU_PLTRST_N | MANAGEMENT | 1V8 | General purpose reset output to Carrier Board |
| P127 | RESET_IN# | RESET_IN_ | AD62 | PMU_RSTBTN_N | MANAGEMENT | PU 10K 1V8 | Reset input from Carrier Board. Carrier drives low to force a Module reset, floats the line otherwise. This signal Shall be level triggered during bootup to allow to stop booting of the module. After bootup it May act as an edge triggered signal |
| P128 | POWER_BTN# | POWER_BTN# | MANAGEMENT | PU 10K 1V8 | Power-button input from Carrier Board. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module. | ||
| P129 | SER0_TX | SOC_COM1_TXD | B43 | LPSS_UART1_TXD | UART0 | 1V8 | Asynchronous Serial Data Output Port 0 |
| P130 | SER0_RX | SOC_COM1_RXD | C43 | LPSS_UART1_RXD | UART0 | 1V8 | Asynchronous Serial Data Input Port 0 |
| P131 | SER0_RTS# | SOC_COM1_RTS_N | A42 | LPSS_UART1_RTS_N | UART0 | 1V8 | Request to Send Handshake Line for Port 0 |
| P132 | SER0_CTS# | SOC_COM1_CTS_N | C42 | LPSS_UART1_CTS_N | UART0 | 1V8 | Clear to Send Handshake Line for Port 0 |
| P133 | GND | PWR/GND | |||||
| P134 | SER1_TX | SOC_COM0_TXD | B45 | LPSS_UART0_TXD | SER1 | 1V8 | Asynchronous Serial Data Output Port 1 |
| P135 | SER1_RX | SOC_COM0_RXD | C45 | LPSS_UART0_RXD | SER1 | 1V8 | Asynchronous Serial Data Input Port 1 |
| P136 | SER2_TX | SOC_COM2_TXD | H41 | LPSS_UART2_TXD | SER2 | 1V8 | Asynchronous Serial Data Output Port 2 |
| P137 | SER2_RX | SOC_COM2_RXD | J41 | LPSS_UART2_RXD | SER2 | 1V8 | Asynchronous Serial Data Input Port 2 |
| P138 | SER2_RTS# | SOC_COM2_RTS_N | L41 | LPSS_UART2_RTS_N | SER2 | 1V8 | Request to Send Handshake Line for Port 2 |
| P139 | SER2_CTS# | SOC_COM2_CTS_N | M41 | LPSS_UART2_CTS_N | SER2 | 1V8 | Clear to Send Handshake Line for Port 2 |
| P140 | SER3_TX | SER3_TX | F61 | SIO_SPI_1_FS1 | SER3 | 1V8 | Asynchronous Serial Data Output Port 3 |
| P141 | SER3_RX | SER3_RX | K55 | SIO_SPI_1_FS0 | SER3 | 1V8 | Asynchronous Serial Data Input Port 3 |
| P142 | GND | PWR/GND | |||||
| P143 | CAN0_TX | ||||||
| P144 | CAN0_RX | ||||||
| P145 | CAN1_TX | ||||||
| P146 | CAN1_RX | ||||||
| P147 | VDD_IN | =D342 | PWR | 5V | |||
| P148 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P149 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P150 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P151 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P152 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P153 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P154 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P155 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P156 | VDD_IN | +5V_SYS | PWR | 5V | |||
| S1 | CSI1_TX+ / I2C_CAM1_CK | CSI1_SCL | AP28 | LPSS_I2C2_SCL | CSI1 | PU 2.2K 1V8 | I2C clock for serial camera data support link or differential data lane |
| S2 | CSI1_TX- / I2C_CAM1_DAT | CSI1_SDA | AP59 | LPSS_I2C2_SDA | CSI1 | PU 2.2K 1V8 | I2C data for serial camera data support link or differential data lane |
| S3 | GND | PWR/GND | |||||
| S4 | RSVD | RSVD | |||||
| S5 | CSI0_TX+ / I2C_CAM0_CK | CSI0_SCL | AM61 | LPSS_I2C1_SCL | CSI0 | PU 2.2K 1V8 | I2C clock for serial camera data support link or differential data lane |
| S6 | CAM_MCK | CAM_MCK | J39 | GPIO_18 | CSI | 1V8 | Master clock output |
| S7 | CSI0_TX- / I2C_CAM0_DAT | CSI0_SDA | AN62 | LPSS_I2C1_SDA | CSI0 | PU 2.2K 1V8 | I2C data for serial camera data support link or differential data lane |
| S8 | CSI0_CK+ | CSI0_CLKP | L23 | MCSI_RX_CLK0_P | CSI0 | CSI0 differential clock input (point to point) | |
| S9 | CSI0_CK- | CSI0_CLKN | J23 | MCSI_RX_CLK0_N | CSI0 | CSI0 differential clock input (point to point) | |
| S10 | GND | PWR/GND | |||||
| S11 | CSI0_RX0+ | CSI0_D0P | M23 | MCSI_RX_DATA0_P | CSI0 | CSI0 differential input | |
| S12 | CSI0_RX0- | CSI0_D0N | P23 | MCSI_RX_DATA0_N | CSI0 | CSI0 differential input | |
| S13 | GND | PWR/GND | |||||
| S14 | CSI0_RX1+ | CSI0_D1P | J21 | MCSI_RX_DATA1_P | CSI0 | CSI0 differential input | |
| S15 | CSI0_RX1- | CSI0_D1N | H21 | MCSI_RX_DATA1_N | CSI0 | CSI0 differential input | |
| S16 | GND | PWR/GND | |||||
| S17 | GBE1_MDI0+ | ETH1_TX0P | ETH1 | Differential Pair Signals for External Transformer | |||
| S18 | GBE1_MDI0- | ETH1_TX0N | ETH1 | Differential Pair Signals for External Transformer | |||
| S19 | GBE1_LINK100# | ETH1_LINK10/100_ | ETH1 | Link Speed Indication LED for GBE1 100Mbps | |||
| S20 | GBE1_MDI1+ | ETH1_TX1P | ETH1 | Differential Pair Signals for External Transformer | |||
| S21 | GBE1_MDI1- | ETH1_TX1N | ETH1 | Differential Pair Signals for External Transformer | |||
| S22 | GBE1_LINK1000# | ETH1_LINK1000_ | ETH1 | Link Speed Indication LED for GBE1 1000Mbps | |||
| S23 | GBE1_MDI2+ | ETH1_TX2P | ETH1 | Differential Pair Signals for External Transformer | |||
| S24 | GBE1_MDI2- | ETH1_TX2N | ETH1 | Differential Pair Signals for External Transformer | |||
| S25 | GND | PWR/GND | |||||
| S26 | GBE1_MDI3+ | ETH1_TX3P | ETH1 | Differential Pair Signals for External Transformer | |||
| S27 | GBE1_MDI3- | ETH1_TX3N | ETH1 | Differential Pair Signals for External Transformer | |||
| S28 | GBE1_CTREF | ETH1 | Center-Tap Reference Voltage for Carrier Board Ethernet Magnetic (if required by the Module GBE PHY) | ||||
| S29 | PCIE_D_TX+ / SERDES_0_TX+ | PCIe3_TXP | P3 | PCIE_P3_TXP | PCIE30 | Differential PCIe link D transmit data pair | |
| S30 | PCIE_D_TX- / SERDES_0_TX- | PCIe3_TXN | P2 | PCIE_P3_TXN | PCIE30 | Differential PCIe link D transmit data pair | |
| S31 | GBE1_LINK_ACT# | ETH1_ACT_ | ETH1 | Link / Activity Indication LED Driven Low on Link (10, 100 or 1000 Mbps) Blinks on Activity | |||
| S32 | PCIE_D_RX+ / SERDES_0_RX+ | PCIe3_RXP | P12 | PCIE_P3_RXP | PCIE30 | Differential PCIe link D receive data pair | |
| S33 | PCIE_D_RX- / SERDES_0_RX- | PCIe3_RXN | P10 | PCIE_P3_RXN | PCIE30 | Differential PCIe link D receive data pair | |
| S34 | GND | PWR/GND | |||||
| S35 | USB4+ | USB4_DP | Y9 | USB2_DP4 | USB4 | USB | USB Differential Data Pairs for Port 4 |
| S36 | USB4- | USB4_DN | Y10 | USB2_DN4 | USB4 | USB | USB Differential Data Pairs for Port 4 |
| S37 | USB3_VBUS_DET | USB Port 3 Host Power Detection. | |||||
| S38 | AUDIO_MCK | AVS_I2S1_MCLK | G62 | AVS_I2S1_MCLK | I2S1 | 1V8 | Master Clock Output to I2S Codec(s) |
| S39 | I2S0_LRCK | AVS_I2S1_WS_SYNC | J62 | AVS_I2S1_WS_SYNC | I2S1 | 1V8 | I2S0 Left and Right Synchronization Clock |
| S40 | I2S0_SDOUT | SOC_AVS_I2S1_SDO | K62 | SOC_AVS_I2S1_SDO | I2S1 | 1V8 | I2S0 Digital Audio Output |
| S41 | I2S0_SDIN | AVS_I2S1_SDI | K61 | AVS_I2S1_SDI | I2S1 | 1V8 | I2S0 Digital Audio Input |
| S42 | I2S0_CK | AVS_I2S1_BCLK | H63 | AVS_I2S1_BCLK | I2S1 | 1V8 | I2S0 Digital Audio Clock |
| S43 | ESPI_ALERT0# | PU 10K 1V8 | ESPI ALERT0 | ||||
| S44 | ESPI_ALERT1# | PU 10K 1V8 | ESPI ALERT1 | ||||
| S45 | MDIO_CLK | 1V8 | MDIO Signals to Configure Possible PHYs | ||||
| S46 | MDIO_DAT | 1V8 | MDIO Signals to Configure Possible PHY | ||||
| S47 | GND | PWR/GND | |||||
| S48 | I2C_GP_CK | SMARC_I2C_GP_CK | AR63 | LPSS_I2C0_SCL | I2C_GP | PU 2.2K 1V8 | General Purpose I2C Clock Signal |
| S49 | I2C_GP_DAT | SMARC_I2C_GP_DAT | AR62 | LPSS_I2C0_SDA | I2C_GP | PU 2.2K 1V8 | General Purpose I2C Data Signal |
| S50 | HDA_SYNC / I2S2_LRCK | HDA_SYNC / I2S2_LRCK | AK58 | AVS_HDA_WS_SYNC | |||
| S51 | HDA_SDO / I2S2_SDOUT | HDA_SDO / I2S2_SDOUT | AM54 | AVS_HDA_SDO | |||
| S52 | HDA_SDI / I2S2_SDIN | HDA_SDI / I2S2_SDIN | AK51 | AVS_HDA_SDI | |||
| S53 | HDA_CK / I2S2_CK | HDA_CK / I2S2_CK | AM48 | AVS_HDA_BCLK | |||
| S54 | SATA_ACT# | SATA_ACT_ | C31 | GPIO_25 | SATA | 3V3 | SATA Activity Indicator |
| S55 | USB5_EN_OC# | USB3-5_EN_OC_ | C55 | USB_OC1_N | USB5 | PU 10k 3.3V | USB Over-Current Sense for Port 5 |
| S56 | ESPI_IO_2 / QSPI_IO_2 | ||||||
| S57 | ESPI_IO_3 / QSPI_IO_3 | ||||||
| S58 | ESPI_RESET# | eSPI | 1V8 | ESPI Reset | |||
| S59 | USB5+ | USB5_DP | AB6 | USB2_DP5 | USB5 | USB | USB Differential Data Pairs for Port 5 |
| S60 | USB5- | USB5_DN | AB7 | USB2_DN5 | USB5 | USB | USB Differential Data Pairs for Port 5 |
| S61 | GND | PWR/GND | |||||
| S62 | USB3_SSTX+ | USB3_SSTXP | K3 | USB3_P1_TXP | USB3 | USB SS | Transmit Signal Differential Pairs for SuperSpeed on Port 3 |
| S63 | USB3_SSTX- | USB3_SSTXN | K2 | USB3_P1_TXN | USB3 | USB SS | Transmit Signal Differential Pairs for SuperSpeed on Port 3 |
| S64 | GND | PWR/GND | |||||
| S65 | USB3_SSRX+ | USB3_SSRXP | F2 | USB3_P1_RXP | USB3 | USB SS | Receive Signal Differential Pairs for SuperSpeed on Port 3 |
| S66 | USB3_SSRX- | USB3_SSRXN | G2 | USB3_P1_RXN | USB3 | USB SS | Receive Signal Differential Pairs for SuperSpeed on Port 3 |
| S67 | GND | PWR/GND | |||||
| S68 | USB3+ | USB3_DP | V9 | USB2_DP3 | USB3 | USB | USB Differential Data Pairs |
| S69 | USB3- | USB3_DM | V7 | USB2_DN3 | USB3 | USB | USB Differential Data Pairs |
| S70 | GND | PWR/GND | |||||
| S71 | USB2_SSTX+ | USB2_SSTXP | J1 | USB3_P0_TXP | USB2 | USB SS | Transmit Signal Differential Pairs for SuperSpeed on Port 2 |
| S72 | USB2_SSTX- | USB2_SSTXN | J2 | USB3_P0_TXN | USB2 | USB SS | Transmit Signal Differential Pairs for SuperSpeed on Port 2 |
| S73 | GND | PWR/GND | |||||
| S74 | USB2_SSRX+ | USB2_SSRXP | K9 | USB3_P0_RXP | USB2 | USB SS | Receive Signal Differential Pairs for SuperSpeed on Port 2 |
| S75 | USB2_SSRX- | USB2_SSRXN | K10 | USB3_P0_RXN | USB2 | USB SS | Receive Signal Differential Pairs for SuperSpeed on Port 2 |
| S76 | PCIE_B_RST# | PCIe_RST_ | AG57 | PMU_PLTRST_N | PCIe1 | 3V3 | PCIe Port B reset output |
| S77 | PCIE_C_RST# | PCIe_RST_ | AG57 | PMU_PLTRST_N | PCIe2 | 3V3 | PCIe Port C reset output |
| S78 | PCIE_C_RX+ / SERDES_1_RX+ | PCIe2_RXP | M5 | PCIE_P2_RXP | PCIE2 | Differential PCIe link C receive data pair | |
| S79 | PCIE_C_RX- / SERDES_1_RX- | PCIe2_RXN | M6 | PCIE_P2_RXN | PCIE2 | Differential PCIe link C receive data pair | |
| S80 | GND | PWR/GND | |||||
| S81 | PCIE_C_TX+ / SERDES_1_TX+ | PCIe2_TXP | T2 | PCIE_P2_TXP | PCIE2 | Differential PCIe link C transmit data pair | |
| S82 | PCIE_C_TX- / SERDES_1_TX- | PCIe2_TXN | T3 | PCIE_P2_TXN | PCIE2 | Differential PCIe link C transmit data pair | |
| S83 | GND | PWR/GND | |||||
| S84 | PCIE_B_REFCK+ | PCIe1_CLKP | C10 | PCIE_CLKOUT1P | Differential PCIe Link B reference clock output | ||
| S85 | PCIE_B_REFCK- | PCIe1_CLKN | A10 | PCIE_CLKOUT1N | Differential PCIe Link B reference clock output | ||
| S86 | GND | PWR/GND | |||||
| S87 | PCIE_B_RX+ | PCIe1_RXP | T10 | PCIE_P1_RXP | PCIE3 | Differential PCIe link B receive data pair | |
| S88 | PCIE_B_RX- | PCIe1_RXN | T12 | PCIE_P1_RXN | PCIE3 | Differential PCIe link B receive data pair | |
| S89 | GND | PWR/GND | |||||
| S90 | PCIE_B_TX+ | PCIE_B_TX+ | R1 | PCIE_P1_TXP | PCIE3 | Differential PCIe link B transmit data pair | |
| S91 | PCIE_B_TX- | PCIE_B_TX- | R2 | PCIE_P1_TXN | PCIE3 | Differential PCIe link B transmit data pair | |
| S92 | GND | PWR/GND | |||||
| S93 | DP0_LANE0+ | DP0_L0+ | AF2 | DDI1_TXP_0 | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S94 | DP0_LANE0- | DP0_L0- | AF3 | DDI1_TXN_0 | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S95 | DP0_AUX_SEL | DP0_AUX_SEL | F39 | GPIO_15 | DP0++ | 1V8 | Auxiliary Selection |
| S96 | DP0_LANE1+ | DP0_L1+ | AD3 | DDI1_TXP_1 | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S97 | DP0_LANE1- | DP0_L1- | AD2 | DDI1_TXN_1 | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S98 | DP0_HPD | DP0_HPD | A50 | GPIO_199 | DP0++ | 1V8 | DP Hot Plug Detect Input |
| S99 | DP0_LANE2+ | DP0_L2+ | AC1 | DDI1_TXP_2 | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S100 | DP0_LANE2- | DP0_L2- | AC2 | DDI1_TXN_2 | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S101 | GND | PWR/GND | |||||
| S102 | DP0_LANE3+ | DP0_L3+ | AB3 | DDI1_TXP_3 | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S103 | DP0_LANE3- | DP0_L3- | AB2 | DDI1_TXN_0 | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S104 | USB3_OTG_ID | USB3 | 3V3 | Input Pin to Announce OTG Device Insertion on USB 2.0 Port | |||
| S105 | DP0_AUX+ | DP0_AUX+ | AK16 | DDI1_AUXP | DP0++ | 3V3 | Primary DP Port Bidirectional Channel used for Link Management and Device Control |
| S106 | DP0_AUX- | DP0_AUX- | AK15 | DDI1_AUXN | DP0++ | 3V3 | Primary DP Port Bidirectional Channel used for Link Management and Device Control |
| S107 | LCD1_BKLT_EN | eDP1 | 1V8 | Secondary LVDS Channel Backlight Enable | |||
| S108 | LVDS1_CK+ / eDP1_AUX+ / DSI1_CLK+ | DSI1 | Secondary DSI Panel Differential Pair Clock Lines | ||||
| S109 | LVDS1_CK- / eDP1_AUX- / DSI1_CLK- | DSI1 | Secondary DSI Panel Differential Pair Clock Lines | ||||
| S110 | GND | PWR/GND | |||||
| S111 | LVDS1_0+ / eDP1_TX0+ / DSI1_D0+ | DSI1 | Secondary DSI Panel Differential Pair Data Lines 0 | ||||
| S112 | LVDS1_0- / eDP1_TX0- / DSI1_D0- | DSI1 | Secondary DSI Panel Differential Pair Data Lines 0 | ||||
| S113 | eDP1_HPD / DSI1_TE | DSI1 | 1V8 | Detection of Hot Plug / Unplug of Secondary eDP Display and Notification of the Link Layer | |||
| S114 | LVDS1_1+ / eDP1_TX1+ / DSI1_D1+ | DSI1 | Secondary DSI Panel Differential Pair Data Lines 1 | ||||
| S115 | LVDS1_1- / eDP1_TX1- / DSI1_D1- | DSI1 | Secondary DSI Panel Differential Pair Data Lines 1 | ||||
| S116 | LCD1_VDD_EN | DSI1 | 1V8 | Secondary Panel Power Enable | |||
| S117 | LVDS1_2+ / eDP1_TX2+ / DSI1_D2+ | DSI1 | Secondary DSI Panel Differential Pair Data Lines 2 | ||||
| S118 | LVDS1_2- / eDP1_TX2- / DSI1_D2- | DSI1 | Secondary DSI Panel Differential Pair Data Lines 2 | ||||
| S119 | GND | PWR/GND | |||||
| S120 | LVDS1_3+ / eDP1_TX3+ / DSI1_D3+ | DSI1 | Secondary DSI Panel Differential Pair Data Lines 3 | ||||
| S121 | LVDS1_3- / eDP1_TX3- / DSI1_D3- | DSI1 | Secondary DSI Panel Differential Pair Data Lines 3 | ||||
| S122 | LCD1_BKLT_PWM | 1V8 | DSI1 | Secondary Panel Brightness Control | |||
| S123 | GPIO13 | GPIO13 | C30 | GPIO_13 | GPIO | 1V8 | GPIO Pin 13 Preferred Output |
| S124 | GND | PWR/GND | |||||
| S125 | LVDS0_0+ / eDP0_TX0+ / DSI0_D0+ | EDP_TX0_DP | AG7 | EDP_TXP_0 | DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S126 | LVDS0_0- / eDP0_TX0- / DSI0_D0- | EDP_TX0_DN | AG9 | EDP_TXN_0 | DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S127 | LCD0_BKLT_EN | PNL0_BKLTEN | B47 | PNL0_BKLTEN | DSI0 | 1V8 | Primary Panel Backlight Enable |
| S128 | LVDS0_1+ / eDP0_TX1+ / DSI0_D1+ | AG12 | AG12 | EDP_TXP_1 | DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S129 | LVDS0_1- / eDP0_TX1- / DSI0_D1- | EDP_TX1_DN | AG10 | EDP_TXN_1 | DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S130 | GND | PWR/GND | |||||
| S131 | LVDS0_2+ / eDP0_TX2+ / DSI0_D2+ | EDP_TX2_DP | AC6 | EDP_TXP_2 | DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S132 | LVDS0_2- / eDP0_TX2- / DSI0_D2- | EDP_TX2_DN | AC5 | EDP_TXN_2 | DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S133 | LCD0_VDD_EN | PNL0_VDDEN | C47 | PNL0_VDDEN | DSI0 | 1V8 | Primary Panel Power Enable |
| S134 | LVDS0_CK+ / eDP0_AUX+ / DSI0_CLK+ | EDP_AUX_P | AH10 | EDP_AUXP | DSI0 | Primary DSI Panel Differential Pair Clock Lines | |
| S135 | LVDS0_CK- / eDP0_AUX- / DSI0_CLK- | EDP_AUX_N | AH9 | EDP_AUXN | DSI0 | Primary DSI Panel Differential Pair Clock Lines | |
| S136 | GND | PWR/GND | |||||
| S137 | LVDS0_3+ / eDP0_TX3+ / DSI0_D3+ | EDP_TX3_DP | AC7 | EDP_TXP_3 | DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S138 | LVDS0_3- / eDP0_TX3- / DSI0_D3- | EDP_TX3_DN | AC9 | EDP_TXN_3 | DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S139 | I2C_LCD_CK | EDP_I2C_LCD_CK | AL62 | LPSS_I2C3_SCL | DSI | PU 2.2K 1V8 | I2C clock to read LCD display EDID EEPROMs |
| S140 | I2C_LCD_DAT | EDP_I2C_LCD_DAT | AM62 | LPSS_I2C3_SDA | DSI | PU 2.2K 1V8 | DDC Data Line Used for Flat Panel Detection and Control |
| S141 | LCD0_BKLT_PWM | PNL0_BKLTCTL | C46 | PNL0_BKLTCTL | DSI0 | 1V8 | Primary Panel Brightness Control |
| S142 | GPIO12 | GPIO12 | E39 | GPIO_12 | GPIO | 1V8 | GPIO Pin 12 Preferred Output |
| S143 | GND | PWR/GND | |||||
| S144 | eDP0_HPD / DSI0_TE | EDP_HPD | P48 | PMC_SPI_FS1 | DSI0 | 1V8 | Primary DSI Panel Tearing Effect Signal |
| S145 | WDT_TIME_OUT# | WDT_TIME_OUT_ | - | WATCHDOG | 1V8 | Watch-Dog-Timer Output, low active | |
| S146 | PCIE_WAKE# | PCIe_WAKE_ | R62 | PCIE_WAKE0_N | PCIE | 3V3 | PCIe wake up interrupt to host – common to PCIe links A, B, C, D |
| S147 | VDD_RTC | VDD_RTC | AC54 | INTRUDER_N | PWR RTC | ||
| S148 | LID# | LID_ | AM52 | ISH_GPIO_8 | MANAGEMENT | PU 1.8K 1V8 | Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in inactive state. Active low, level sensitive. Should be de-bounced on the Module. |
| S149 | SLEEP# | SLEEP_ | AM55 | ISH_GPIO_7 | MANAGEMENT | PU 1.8K 1V8 | Sleep indicator from Carrier Board. May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module. |
| S150 | VIN_PWR_BAD# | VIN_PWR_BAD_ | AM49 | ISH_GPIO_5 | MANAGEMENT | PU 10K 5V | Power bad indication from Carrier Board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall not be enabled while this signal is held low by the Carrier. |
| S151 | CHARGING# | CHARGING_ | H35 | GPIO_29 | MANAGEMENT | PU 10K 1V8 | Held low by Carrier during battery charging. Carrier to float the line when charge is complete. |
| S152 | CHARGER_PRSNT# | CHARGER_PRSNT_ | C37 | GPIO_30 | MANAGEMENT | PU 10K 1V8 | Held low by Carrier if DC input for battery charger is present |
| S153 | CARRIER_STBY# | CARRIER_STBY_ | AC62 | PMU_SLP_S3_N | MANAGEMENT | 1V8 | The Module shall drive this signal low when the system is in a standby power state. |
| S154 | CARRIER_PWR_ON | CARRIER_PWR_ON | AK54 | PMU_SLP_S4_N | MANAGEMENT | 1V8 | Carrier Board circuits (apart from power management and power path circuits) should not be powered up until the Module asserts the CARRIER_PWR_ON signal. |
| S155 | FORCE_RECOV# | FORCE_RECOVER_ | A26 | GPIO_22 | BOOT | PU 10K 1V8 | Low on this pin allows nonprotected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode – such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier. |
| S156 | BATLOW# | BATLOW_ | AM57 | ISH_GPIO_6 | MANAGEMENT | PU 10K 1V8 | Battery low indication to Module. Carrier to float the line in inactive state |
| S157 | TEST# | TEST_ | AK57 | ISH_GPIO_9 | MANAGEMENT | PU 10K 1V8 | Held Low by Carrier to Invoke Module Vendor Specific Test Functions |
| S158 | GND | PWR/GND |