| Pin # | SMARC Pin Name | Board Signal | CPU Pin | CPU Functions | Group | I/O Level | Comments |
|---|---|---|---|---|---|---|---|
| P1 | SMB_ALERT# | SMB_ALERT_ | AD23 | LITCPU_AVS SPI3_CLK_M2 GPIO0_D3_u |
MANAGEMENT | PU 2k2 | SMBus Alert# (Interrupt) Signal |
| P2 | GND | PWR/GND | |||||
| P3 | CSI1_CK+ | CSI1_CLKP | AJ33 | MIPI_CSI0_CLK0P | CSI1 | CSI1 differential clock input (point to point) | |
| P4 | CSI1_CK- | CSI1_CLKN | AJ34 | MIPI_CSI0_CLK0N | CSI1 | CSI1 differential clock input (point to point) | |
| P5 | GBE1_SDP | NC | |||||
| P6 | GBE0_SDP | NC | |||||
| P7 | CSI1_RX0+ | CSI1_RX0P | AJ33 | MIPI_CSI0_D0P | CSI1 | CSI1 differential input (point to point) | |
| P8 | CSI1_RX0- | CSI1_RX0N | AJ34 | MIPI_CSI0_D0N | CSI1 | CSI1 differential input (point to point) | |
| P9 | GND | PWR/GND | |||||
| P10 | CSI1_RX1+ | CSI1_RX1P | AH33 | MIPI_CSI0_D1P | CSI1 | CSI1 differential input (point to point) | |
| P11 | CSI1_RX1- | CSI1_RX1N | AH34 | MIPI_CSI0_D1N | CSI1 | CSI1 differential input (point to point) | |
| P12 | GND | PWR/GND | |||||
| P13 | CSI1_RX2+ | CSI1_RX2P | AK33 | MIPI_CSI0_D2P | CSI1 | CSI1 differential input (point to point) | |
| P14 | CSI1_RX2- | CSI1_RX2N | AK34 | MIPI_CSI0_D2N | CSI1 | CSI1 differential input (point to point) | |
| P15 | GND | PWR/GND | |||||
| P16 | CSI1_RX3+ | CSI1_RX3P | AL33 | MIPI_CSI0_D3P | CSI1 | ||
| P17 | CSI1_RX3- | CSI1_RX3N | AL34 | MIPI_CSI0_D3N | CSI1 | ||
| P18 | GND | PWR/GND | |||||
| P19 | GBE0_MDI3- | ETH0_TX3N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P20 | GBE0_MDI3+ | ETH0_TX3P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P21 | GBE0_LINK100# | ETH0_LINK10/100_ | - | GBE0 | 3V3 | Link Speed Indication LED for GBE0 100Mbps | |
| P22 | GBE0_LINK1000# | ETH0_LINK1000_ | - | GBE0 | 3V3 | Link Speed Indication LED for GBE0 1000Mbps | |
| P23 | GBE0_MDI2- | ETH0_TX2N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P24 | GBE0_MDI2+ | ETH0_TX2P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P25 | GBE0_LINK_ACT# | ETH0_ACT_ | - | GBE0 | 3V3 | Link / Activity Indication LED Driven Low on Link (10, 100 or 1000 Mbps) Blinks on Activity | |
| P26 | GBE0_MDI1- | ETH0_TX1N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P27 | GBE0_MDI1+ | ETH0_TX1P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P28 | GBE0_CTREF | ETH_CTREF | AH25 | CIF_D9 FSPI_CS1N_M2 PCIE30X4_WAKEN_M2 HDMI_TX1_SDA_M1 CAN2_TX_M0 UART5_RX_M1 SPI3_CS1_M3 GPIO3_C5_U |
GBE0 | 0…3V3 | Center-Tap Reference Voltage for Carrier Board Ethernet Magnetic (if required by the Module GBE PHY) |
| P29 | GBE0_MDI0- | ETH0_TX0N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P30 | GBE0_MDI0+ | ETH0_TX0P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P31 | SPI0_CS1# | SPI0_CS1_ | E25 | PCIE30X1_0_CLKREQN_M2 UART7_TX_M2 SPI0_CS1_M2 GPIO1_B5_u |
SPI | 1V8 | SPI Master Chip Select 1 |
| P32 | GND | PWR/GND | |||||
| P33 | SDIO_WP | SDMMC0_WP | AE24 | REFCLK_OUT GPIO0_A0_d |
SDIO | 1V8 or 3V3 | SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards. |
| P34 | SDIO_CMD | SDMMC0_CMD | AE2 | SDMMC_CMD PDM1_CLK1_M0 MCU_JTAG_TCK_M0 UART5_RX_M0 PWM7_IR_M1 GPIO4_D4_u |
SDIO | 1V8 or 3V3 | SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode. |
| P35 | SDIO_CD# | SDMMC0_DET_ | P31 | SDMMC_DET GPIO0_A4_u |
SDIO | 1V8 or 3V3 | SDIO Card Detect. This signal indicates when a SDIO/MMC card is present. |
| P36 | SDIO_CK | SDMMC0_CLK | AE1 | SDMMC_CLK PDM1_CLK0_M0 TEST_CLKOUT_M0 MCU_JTAG_TMS_M0 UART5_TX_M0 GPIO4_D5_d |
SDIO | 1V8 or 3V3 | SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. |
| P37 | SDIO_PWR_EN | SDMMC0_PWR_EN | AA27 | HDMI_TX0_HPD_M1 PCIE30X2_PERSTN_M2 HDMI_RX_HPDOUT_M1 MCU_JTAG_TCK_M1 UART9_RX_M2 SPI0_CS0_M3 GPIO3_D4_D |
SDIO | 3V3 | DIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device. |
| P38 | GND | PWR/GND | |||||
| P39 | SDIO_D0 | SDMMC0_D0 | AD2 | UART2_TX_M1 | SDIO | 1V8 or 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P40 | SDIO_D1 | SDMMC0_D1 | AD1 | SDMMC_D1 PDM1_SDI2_M0 JTAG_TMS_M1 I2C3_SDA_M4 UART2_RX_M1 PWM9_M1 GPIO4_D1_u |
SDIO | 1V8 or 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P41 | SDIO_D2 | SDMMC0_D2 | AF2 | SDMMC_D2 PDM1_SDI1_M0 JTAG_TCK_M0 I2C8_SCL_M0 UART5_CTSN_M0 GPIO4_D2_u |
SDIO | 1V8 or 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P42 | SDIO_D3 | SDMMC0_D3 | AF1 | SDMMC_D3 PDM1_SDI0_M0 JTAG_TMS_M0 I2C8_SDA_M0 UART5_RTSN_M0 PWM10_M1 GPIO4_D3_u |
SDIO | 1V8 or 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P43 | SPI0_CS0# | SPI0_CS0_ | E24 | PDM1_CLK0_M1 PCIE30X1_0_PERSTN_M2 UART7_RX_M2 SPI0_CS0_M2 GPIO1_B4_u |
SPI | 1V8 | SPI Master Chip Select 0 |
| P44 | SPI0_CK | SPI0_CLK | AE1 | SDMMC_CLK PDM1_CLK0_M0 TEST_CLKOUT_M0 MCU_JTAG_TMS_M0 UART5_TX_M0 GPIO4_D5_d |
SPI | 1V8 | SPI Clock |
| P45 | SPI0_DIN | SPI0_MISO | D25 | PDM1_SDI2_M1 PCIE30X4_WAKEN_M3 SPI0_MISO_M2 GPIO1_B1_d |
SPI | 1V8 | SPI Master input / Slave output |
| P46 | SPI0_DO | SPI0_MOSI | D26 | PDM1_SDI3_M1 PCIE30X4_PERSTN_M3 UART4_RX_M2 SPI0_MOSI_M2 GPIO1_B2_d |
SPI | 1V8 | SPI Master output / Slave input |
| P47 | GND | PWR/GND | |||||
| P48 | SATA_TX+ | SATA_TXP | M34 | PCIE20_0_TXP SATA30_0_TXP |
SATA | Serial ATA Channel 0 Transmit Output Differential Pair | |
| P49 | SATA_TX- | SATA_TXN | M33 | PCIE20_0_TXN SATA30_0_TXN |
SATA | Serial ATA Channel 0 Transmit Output Differential Pair | |
| P50 | GND | PWR/GND | |||||
| P51 | SATA_RX+ | SATA_RXP | N33 | PCIE20_0_RXP SATA30_0_RXP |
SATA | Serial ATA Channel 0 Receive Input Differential Pair | |
| P52 | SATA_RX- | SATA_RXN | N34 | PCIE20_0_RXN SATA30_0_RXN |
SATA | Serial ATA Channel 0 Receive Input Differential Pair | |
| P53 | GND | PWR/GND | |||||
| P54 | ESPI_CS0# / SPI1_CS0# / QSPI_CS0# | ||||||
| P55 | ESPI_CS1# / SPI1_CS1# / QSPI_CS1# | ||||||
| P56 | ESPI_CK / SPI1_CK / QSPI_CK | ||||||
| P57 | ESPI_IO_1 / SPI1_DIN / QSPI_IO_1 | ||||||
| P58 | ESPI_IO_0 / SPI1_DO / QSPI_IO_0 | ||||||
| P59 | GND | PWR/GND | |||||
| P60 | USB0+ | USB0_D+ | AL12 | TYPEC0_USB20_OTG_DP | USB0 | USB | USB Differential Data Pairs for Port 0 |
| P61 | USB0- | USB0_D- | AM12 | TYPEC0_USB20_OTG_DM | USB0 | USB | USB Differential Data Pairs for Port 0 |
| P62 | USB0_EN_OC# | USB20_EN_OC_ | AG23 | CIF_D13 PCIE20X1_2_PERSTN_M0 HDMI_RX_CEC_M1 UART4_TX_M1 PWM9_M2 SPI0_MISO_M3 GPIO3_D1_D |
USB0 | PU 10k 3.3V | USB Over-Current Sense for Port 0 |
| P63 | USB0_VBUS_DET | TYPEC0_USB20_VBUSDET | AM14 | TYPEC0_USB20_VBUSDET | USB0 | 5V | USB Port 0 Host Power Detection |
| P64 | USB0_OTG_ID | USB0_OTG_ID | AL14 | USB0_OTG_ID | USB0 | PU 10k 1.8V | |
| P65 | USB1+ | USB1_DP | USB1 | USB | USB Differential Data Pairs for Port 1 | ||
| P66 | USB1- | USB1_DN | USB1 | USB | USB Differential Data Pairs for Port 1 | ||
| P67 | USB1_EN_OC# | USB20_EN_OC_ | AG23 | CIF_D13 PCIE20X1_2_PERSTN_M0 HDMI_RX_CEC_M1 UART4_TX_M1 PWM9_M2 SPI0_MISO_M3 GPIO3_D1_D |
USB1 | PU 10k 3.3V | USB Over-Current Sense for Port 1 |
| P68 | GND | PWR/GND | |||||
| P69 | USB2+ | USB2_DP | USB2 | USB | USB Differential Data Pairs for Port 2 | ||
| P70 | USB2- | USB2_DN | USB2 | USB | USB Differential Data Pairs for Port 2 | ||
| P71 | USB2_EN_OC# | USB30_EN_OC_ | AB28 | PCIE30X4_BUTTON_RSTN DP1_HPDIN_M0 MCU_JTAG_TMS_M1 UART9_TX_M2 PWM11_IR_M3 SPI0_CS1_M3 GPIO3_D5_D |
USB2 | PU 10k 3.3V | USB Over-Current Sense for Port 2 |
| P72 | RSVD | RSVD | |||||
| P73 | RSVD | RSVD | |||||
| P74 | USB3_EN_OC# | USB30_EN_OC_ | AB28 | PCIE30X4_BUTTON_RSTN DP1_HPDIN_M0 MCU_JTAG_TMS_M1 UART9_TX_M2 PWM11_IR_M3 SPI0_CS1_M3 GPIO3_D5_D |
USB3 | PU 10k 3.3V | USB Over-Current Sense for Port 3 |
| P75 | PCIE_A_RST# | PCIe_RST_ | AG26 | CIF_D10 PCIE30X4_PERSTN_M2 HDMI_TX1_SCL_M1 SPI3_MISO_M3 GPIO3_C6_u |
PCIe0 | 3V3 | PCIe Port A reset output |
| P76 | USB4_EN_OC# | USB20_EN_OC_ | AG23 | CIF_D13 PCIE20X1_2_PERSTN_M0 HDMI_RX_CEC_M1 UART4_TX_M1 PWM9_M2 SPI0_MISO_M3 GPIO3_D1_D |
USB4 | PU 10k 3.3V | USB Over-Current Sense for Port 4 |
| P77 | PCIE_B_CKREQ# | PCIe1_CLKREQ_ | - | PCIe1 | PCIe Port B clock request | ||
| P78 | PCIE_A_CKREQ# | PCIe0_CLKREQ_ | - | PCIe0 | PCIe Port A clock request | ||
| P79 | GND | PWR/GND | |||||
| P80 | PCIE_C_REFCK+ | PCIe2_CLKP | - | PCIE20 | Differential PCIe Link C reference clock output | ||
| P81 | PCIE_C_REFCK- | PCIe2_CLKP | - | PCIE20 | Differential PCIe Link C reference clock output | ||
| P82 | GND | PWR/GND | |||||
| P83 | PCIE_A_REFCK+ | PCIe0_CLKP | - | PCIe0 | Differential PCIe Link A reference clock output | ||
| P84 | PCIE_A_REFCK- | PCIe0_CLKN | - | PCIe0 | Differential PCIe Link A reference clock output | ||
| P85 | GND | PWR/GND | |||||
| P86 | PCIE_A_RX+ | PCIe0_RXP | G33 | PCIE30_PORT0_RX0P | PCIE30 | Differential PCIe link A receive data pair | |
| P87 | PCIE_A_RX- | PCIe0_RXN | G34 | PCIE30_PORT0_RX0N | PCIE30 | Differential PCIe link A receive data pair | |
| P88 | GND | PWR/GND | |||||
| P89 | PCIE_A_TX+ | PCIe0_TXP | D32 | PCIE30_PORT0_TX0P | PCIE30 | Differential PCIe link A transmit data pair | |
| P90 | PCIE_A_TX- | PCIe0_TXN | D33 | PCIE30_PORT0_TX0N | PCIE30 | Differential PCIe link A transmit data pair | |
| P91 | GND | PWR/GND | |||||
| P92 | HDMI_D2+ / DP1_LANE0+ | HDMI_D2+ | AN6 | HDMI_TX1_D2P eDP_TX1_D2P |
HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P93 | HDMI_D2- / DP1_LANE0- | HDMI_D2- | AP6 | HDMI_TX1_D2N eDP_TX1_D2N |
HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P94 | GND | PWR/GND | |||||
| P95 | HDMI_D1+ / DP1_LANE1+ | HDMI_D1+ | AM5 | HDMI_TX1_D1P eDP_TX1_D1P |
HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P96 | HDMI_D1- / DP1_LANE1- | HDMI_D1- | AN5 | HDMI_TX1_D1N eDP_TX1_D1N |
HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P97 | GND | PWR/GND | |||||
| P98 | HDMI_D0+ / DP1_LANE2+ | HDMI_D0+ | AN4 | HDMI_TX1_D0P eDP_TX1_D0P |
HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P99 | HDMI_D0- / DP1_LANE2- | HDMI_D0- | AP4 | HDMI_TX1_D0N eDP_TX1_D0N |
HDMI/DP | HDMI Port, Differential Pair Data Lines | |
| P100 | GND | PWR/GND | |||||
| P101 | HDMI_CK+ / DP1_LANE3+ | HDMI_CLK+ | AM3 | HDMI_TX1_D3P eDP_TX1_D3P |
HDMI/DP | HDMI Port, Differential Pair Clock Lines | |
| P102 | HDMI_CK- / DP1_LANE3- | HDMI_CLK- | AN3 | HDMI_TX1_D3N eDP_TX1_D3N |
HDMI/DP | HDMI Port, Differential Pair Clock Lines | |
| P103 | GND | PWR/GND | |||||
| P104 | HDMI_HPD / DP1_HPD | HDMI_HPD | C24 | HDMI_TX1_HPD_M0 SPI2_CLK_M0 GPIO1_A6_d |
HDMI/DP | PD 1M 1V8 | HDMI Hot Plug Active High Detection Signal that Serves as an Interrupt Request |
| P105 | HDMI_CTRL_CK / DP1_AUX+ | HDMI_SCL_DP1_AUX+ | AB30 | GMAC0_PPSTRING FSPI_CS1N_M1 HDMI_TX1_SCL_M0 I2C4_SCL_M1 UART7_TX_M0 GPIO2_B5_u |
HDMI/DP | PU 1V8 | I2C_CLK Line Dedicated to HDMI / DP1_AUX+ |
| P106 | HDMI_CTRL_DAT / DP1_AUX- | HDMI_SDA_DP1_AUX- | AB31 | GMAC0_PTP_REFCLK FSPI_CS0N_M1 HDMI_TX1_SDA_M0 I2C4_SDA_M1 UART7_RX_M0 GPIO2_B4_u |
HDMI/DP | PU 1V8 | I2C_DAT Line Dedicated to HDMI / DP1_AUX- |
| P107 | DP1_AUX_SEL | DP1_AUX_SEL | DP1++_HDMI | 1V8 | Strapping Signal to Enable Either HDMI or DP Output | ||
| P108 | GPIO0 / CAM0_PWR# | GPIO0_SPI0_CLK | AL27 | CIF_D6 BT1120_D6 I2S1_SDI1_M0 PCIE30X2_CLKREQN_M1 I2C5_SCL_M2 UART3_RX_M2 SPI2_CLK_M1 GPIO4_A6_d |
GPIO | PU 1V8 | GPIO Pin 0 Preferred Output |
| P109 | GPIO1 / CAM1_PWR# | GPIO1/CSI1_PWR_ | AL28 | CIF_D4 BT1120_D4 PCIE30X1_0_WAKEN_M1 I2C3_SCL_M2 UART0_RX_M2 SPI2_MISO_M1 GPIO4_A4_d |
GPIO | PU 1V8 | GPIO Pin 1 Preferred Output |
| P110 | GPIO2 / CAM0_RST# | GPIO2/CSI0_RST_ | AK27 | CIF_D5 BT1120_D5 I2S1_SDI0_M0 PCIE30X1_0_PERSTN_M1 I2C3_SDA_M2 UART3_TX_M2 SPI2_MOSI_M1 GPIO4_A5_d |
GPIO | PU 1V8 | GPIO Pin 2 Preferred Output |
| P111 | GPIO3 / CAM1_RST# | GPIO3/CSI1_RST_ | AM27 | CIF_D7 BT1120_D7 I2S1_SDI2_M0 PCIE30X2_WAKEN_M1 I2C5_SDA_M2 SPI2_CS0_M1 GPIO4_A7_d |
GPIO | PU 1V8 | GPIO Pin 3 Preferred Output |
| P112 | GPIO4 / HDA_RST# | GPIO4/HDA_RST_ | AF33 | GMAC0_TXER I2C0_SDA_M1 UART7_CTSN_M0 PWM7_IR_M3 SPI3_CLK_M0 GPIO4_C6_D |
GPIO | PU 1V8 | GPIO Pin 4 Preferred Output |
| P113 | GPIO5 / PWM_OUT | GPIO5/PWM_OUT | T29 | I2S1_SDI1_M1 NPU_AVS UART0_RTSN PWM5_M1 SPI0_CLK_M0 PCIE30X4_CLKREQN_M0 SATA_CP_POD GPIO0_C6_U |
GPIO | PU 1V8 | GPIO Pin 5 Preferred Output |
| P114 | GPIO6 / TACHIN | GPIO6/TACHIN | AE30 | CLK32K_OUT1 GPIO2_C5_D |
GPIO | PU 1V8 | GPIO Pin 6 Preferred Output |
| P115 | GPIO7 | GPIO7 | AM29 | CIF_D2 BT1120_D2 I2S1_LRCK_M0 PCIE30X1_1_PERSTN_M1 SPI0_CLK_M1 GPIO4_A2_D |
GPIO | PU 1V8 | GPIO Pin 7 Preferred Output |
| P116 | GPIO8 | GPIO8 | A26 | VOP_POST_EMPTY I2C4_SDA_M3 UART6_RTSN_M1 PWM0_M2 SPI4_CLK_M2 GPIO1_A2_D |
GPIO | PU 1V8 | GPIO Pin 8 Preferred Output |
| P117 | GPIO9 | GPIO9 | A24 | PCIE30X1_1_CLKREQN_M2 DP0_HPDIN_M2 I2C2_SDA_M4 UART6_RX_M1 SPI4_MISO_M2 GPIO1_A0_D |
GPIO | PU 1V8 | GPIO Pin 9 Preferred Output |
| P118 | GPIO10 | GPIO10 | A25 | PCIE30X1_1_WAKEN_M2 DP1_HPDIN_M2 SATA1_ACT_LED_M1 I2C2_SCL_M4 UART6_TX_M1 SPI4_MOSI_M2 GPIO1_A1_D |
GPIO | PU 1V8 | GPIO Pin 10 Preferred Output |
| P119 | GPIO11 | GPIO11 | A27 | HDMI_TX1_SDA_M2 I2C4_SCL_M3 UART6_CTSN_M1 PWM1_M2 SPI4_CS0_M2 GPIO1_A3_D |
GPIO | PU 1V8 | GPIO Pin 11 Preferred Output |
| P120 | GND | PWR/GND | |||||
| P121 | I2C_PM_CK | SMARC_I2C_PM_CK | G27 | I2C3_SCL_M0 UART3_TX_M0 SPI4_MOSI_M0 GPIO1_C1_Z |
MANAGEMENT | PU 2.2K 1V8 | Power management I2C bus CLK |
| P122 | I2C_PM_DAT | SMARC_I2C_PM_DAT | G29 | I2C3_SDA_M0 UART3_RX_M0 SPI4_MISO_M0 GPIO1_C0_Z |
MANAGEMENT | PU 2.2K 1V8 | Power management I2C bus DATA |
| P123 | BOOT_SEL0# | BOOT_SEL0_ | - | BOOT | PU 10K 1V8 | Input straps determine the Module boot device | |
| P124 | BOOT_SEL1# | BOOT_SEL1_ | - | BOOT | PU 10K 1V8 | Input straps determine the Module boot device | |
| P125 | BOOT_SEL2# | BOOT_SEL2_ | - | BOOT | PU 10K 1V8 | Input straps determine the Module boot device | |
| P126 | RESET_OUT# | RESET_OUT_ | - | MANAGEMENT | 1V8 | General purpose reset output to Carrier Board | |
| P127 | RESET_IN# | RESET_IN_ | - | MANAGEMENT | PU 10K 1V8 | Reset input from Carrier Board. Carrier drives low to force a Module reset, floats the line otherwise. This signal Shall be level triggered during bootup to allow to stop booting of the module. After bootup it May act as an edge triggered signal | |
| P128 | POWER_BTN# | POWER_BTN# | MANAGEMENT | PU 10K 1V8 | Power-button input from Carrier Board. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module. | ||
| P129 | SER0_TX | SER0_TX | AL26 | CIF_CLKOUT BT1120_D10 I2S1_SDO3_M0 PCIE30X4_CLKREQN_M1 DP0_HPDIN_M0 SPDIF0_TX_M1 UART9_TX_M1 PWM11_IR_M1 GPIO4_B4_u |
UART0 | 1V8 | Asynchronous Serial Data Output Port 0 |
| P130 | SER0_RX | SER0_RX | AJ26 | CIF_CLKOUT BT1120_D10 I2S1_SDO3_M0 PCIE30X4_CLKREQN_M1 DP0_HPDIN_M0 SPDIF0_TX_M1 UART9_TX_M1 PWM11_IR_M1 GPIO4_B4_u BT1120_D11 PCIE30X4_WAKEN_M1 HDMI_RX_CEC_M0 SATA1_ACT_LED_M0 UART9_RX_M1 PWM12_M1 SPI3_MISO_M1 GPIO4_B5_d |
UART0 | 1V8 | Asynchronous Serial Data Input Port 0 |
| P131 | SER0_RTS# | SER0_RTS_ | AK30 | CIF_D0 BT1120_D0 I2S1_MCLK_M0 PCIE30X1_1_CLKREQN_M1 UART9_RTSN_M1 SPI0_MISO_M1 GPIO4_A0_d |
UART0 | 1V8 | Request to Send Handshake Line for Port 0 |
| P132 | SER0_CTS# | SER0_CTS_ | AL30 | CIF_D1 BT1120_D1 I2S1_SCLK_M0 PCIE30X1_1_WAKEN_M1 UART9_CTSN_M1 SPI0_MOSI_M1 GPIO4_A1_d |
UART0 | 1V8 | Clear to Send Handshake Line for Port 0 |
| P133 | GND | PWR/GND | |||||
| P134 | SER1_TX | DBG_UART2_TX | P29 | I2S1_MCLK_M1 JTAG_TCK_M2 I2C1_SCL_M0 UART2_TX_M0 PCIE30X1_1_CLKREQN_M0 GPIO0_B5_d |
SER1 | 1V8 | Asynchronous Serial Data Output Port 1 |
| P135 | SER1_RX | DBG_UART2_RX | R29 | I2S1_SCLK_M1 JTAG_TMS_M2 I2C1_SDA_M0 UART2_RX_M0 PCIE30X1_1_WAKEN_M0 GPIO0_B6_d |
SER1 | 1V8 | Asynchronous Serial Data Input Port 1 |
| P136 | SER2_TX | SER2_TX | E26 | MIPI_CAMERA1_CLK_M0 SPDIF0_TX_M0 PCIE30X2_WAKEN_M3 HDMI_RX_HPDOUT_M2 I2C5_SCL_M3 UART1_TX_M1 GPIO1_B6_U |
SER2 | 1V8 | Asynchronous Serial Data Output Port 2 |
| P137 | SER2_RX | SER2_RX | E27 | MIPI_CAMERA2_CLK_M0 SPDIF1_TX_M0 PCIE30X2_PERSTN_M3 HDMI_RX_CEC_M2 SATA2_ACT_LED_M1 I2C5_SDA_M3 UART1_RX_M1 PWM13_M2 GPIO1_B7_U |
SER2 | 1V8 | Asynchronous Serial Data Input Port 2 |
| P138 | SER2_RTS# | SER2_RTS_ | F24 | MIPI_CAMERA3_CLK_M0 HDMI_RX_SCL_M2 I2C8_SCL_M2 UART1_RTSN_M1 PWM14_M2 GPIO1_D6_U |
SER2 | 1V8 | Request to Send Handshake Line for Port 2 |
| P139 | SER2_CTS# | SER2_CTS_ | F25 | MIPI_CAMERA4_CLK_M0 PCIE30X2_CLKREQN_M3 HDMI_RX_SDA_M2 I2C8_SDA_M2 UART1_CTSN_M1 PWM15_IR_M3 GPIO1_D7_U |
SER2 | 1V8 | Clear to Send Handshake Line for Port 2 |
| P140 | SER3_TX | SER3_TX | F28 | I2S0_SDO3 I2S0_SDI2 PDM0_SDI2_M0 I2C1_SCL_M4 UART4_TX_M0 PWM0_M1 SPI1_CLK_M2 GPIO1_D2_D |
SER3 | 1V8 | Asynchronous Serial Data Output Port 3 |
| P141 | SER3_RX | SER3_RX | E28 | I2S0_SDI1 PDM0_SDI3_M0 I2C1_SDA_M4 UART4_RX_M0 PWM1_M1 SPI1_CS0_M2 GPIO1_D3_D |
SER3 | 1V8 | Asynchronous Serial Data Input Port 3 |
| P142 | GND | PWR/GND | |||||
| P143 | CAN0_TX | CAN0_TX | T28 | I2S1_LRCK_M1 PWM0_M0 I2C2_SCL_M0 SPI0_CS1_M0 PCIE30X1_1_PERSTN_M0 GPIO0_B7_d |
CAN1 | 1V8 | CAN Port 1 Transmit Output |
| P144 | CAN0_RX | CAN0_RX | T31 | PDM0_CLK0_M1 PWM1_M0 I2C2_SDA_M0 SPI0_MOSI_M0 PCIE30X1_0_CLKREQN_M0 GPIO0_C0_d |
CAN1 | 1V8 | CAN Port 1 Receive Input |
| P145 | CAN1_TX | CAN1_TX | AM25 | CIF_VSYNC BT1120_D9 I2S1_SDO2_M0 PCIE20X1_2_BUTTON_RSTN I2C7_SDA_M3 UART8_CTSN_M0 PWM15_IR_M1 GPIO4_B3_u |
|||
| P146 | CAN1_RX | CAN1_RX | AK25 | CIF_HREF BT1120_D8 I2S1_SDO1_M0 PCIE30X1_1_BUTTON_RSTN I2C7_SCL_M3 UART8_RTSN_M0 PWM14_M1 SPI0_CS0_M1 GPIO4_B2_u |
|||
| P147 | VDD_IN | =D342 | PWR | 5V | |||
| P148 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P149 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P150 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P151 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P152 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P153 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P154 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P155 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P156 | VDD_IN | +5V_SYS | PWR | 5V | |||
| S1 | CSI1_TX+ / I2C_CAM1_CK | CAM1_CK | AJ27 | BT1120_D12 PCIE30X4_PERSTN_M1 HDMI_RX_HPDOUT_M0 SATA0_ACT_LED_M0 I2C5_SCL_M1 PWM13_M1 SPI3_MOSI_M1 GPIO4_B6_D |
CSI1 | PU 2.2K 1V8 | I2C clock for serial camera data support link or differential data lane |
| S2 | CSI1_TX- / I2C_CAM1_DAT | CAM1_DAT | AJ28 | BT1120_D13 PCIE20X1_2_CLKREQN_M1 HDMI_TX0_SCL_M0 I2C5_SDA_M1 SPI3_CLK_M1 GPIO4_B7_U |
CSI1 | PU 2.2K 1V8 | I2C data for serial camera data support link or differential data lane |
| S3 | GND | PWR/GND | |||||
| S4 | RSVD | RSVD | |||||
| S5 | CSI0_TX+ / I2C_CAM0_CK | CAM0_CK | F26 | I2S0_SDO1 I2C7_SCL_M0 UART6_TX_M2 SPI1_MISO_M2 GPIO1_D0_d |
CSI0 | PU 2.2K 1V8 | I2C clock for serial camera data support link or differential data lane |
| S6 | CAM_MCK | CAM0_MCK | AL24 | MIPI_CAMERA0_CLK_M0 SPDIF1_TX_M1 I2S1_SDO0_M0 PCIE30X1_0_BUTTON_RSTN SATA2_ACT_LED_M0 I2C6_SCL_M3 UART8_RX_M0 SPI0_CS1_M1 GPIO4_B1_U |
CSI | 1V8 | Master clock output |
| S7 | CSI0_TX- / I2C_CAM0_DAT | CAM0_DAT | F27 | I2S0_SDO2 I2S0_SDI3 PDM0_SDI1_M0 I2C7_SDA_M0 UART6_RX_M2 SPI1_MOSI_M2 GPIO1_D1_d |
CSI0 | PU 2.2K 1V8 | I2C data for serial camera data support link or differential data lane |
| S8 | CSI0_CK+ | CSI0_CLKP | AJ31 | MIPI_CSI1_CLK0P | CSI0 | CSI0 differential clock input (point to point) | |
| S9 | CSI0_CK- | CSI0_CLKN | AJ32 | MIPI_CSI1_CLK0N | CSI0 | CSI0 differential clock input (point to point) | |
| S10 | GND | PWR/GND | |||||
| S11 | CSI0_RX0+ | CSI0_RX0P | AG31 | MIPI_CSI1_D0P | CSI0 | CSI0 differential input | |
| S12 | CSI0_RX0- | CSI0_RX0N | AG32 | MIPI_CSI1_D0N | CSI0 | CSI0 differential input | |
| S13 | GND | PWR/GND | |||||
| S14 | CSI0_RX1+ | CSI0_RX1P | AH31 | MIPI_CSI1_D1P | CSI0 | CSI0 differential input | |
| S15 | CSI0_RX1- | CSI0_RX1N | AH32 | MIPI_CSI1_D1N | CSI0 | CSI0 differential input | |
| S16 | GND | PWR/GND | |||||
| S17 | GBE1_MDI0+ | ETH1_TX0P | - | ETH1 | Differential Pair Signals for External Transformer | ||
| S18 | GBE1_MDI0- | ETH1_TX0N | ETH1 | Differential Pair Signals for External Transformer | |||
| S19 | GBE1_LINK100# | ETH1_LINK10/100_ | ETH1 | Link Speed Indication LED for GBE1 100Mbps | |||
| S20 | GBE1_MDI1+ | ETH1_TX1P | ETH1 | Differential Pair Signals for External Transformer | |||
| S21 | GBE1_MDI1- | ETH1_TX1N | ETH1 | Differential Pair Signals for External Transformer | |||
| S22 | GBE1_LINK1000# | ETH1_LINK1000_ | ETH1 | Link Speed Indication LED for GBE1 1000Mbps | |||
| S23 | GBE1_MDI2+ | ETH1_TX2P | ETH1 | Differential Pair Signals for External Transformer | |||
| S24 | GBE1_MDI2- | ETH1_TX2N | ETH1 | Differential Pair Signals for External Transformer | |||
| S25 | GND | PWR/GND | |||||
| S26 | GBE1_MDI3+ | ETH1_TX3P | ETH1 | Differential Pair Signals for External Transformer | |||
| S27 | GBE1_MDI3- | ETH1_TX3N | ETH1 | Differential Pair Signals for External Transformer | |||
| S28 | GBE1_CTREF | ETH_CTREF | AH25 | CIF_D9 FSPI_CS1N_M2 PCIE30X4_WAKEN_M2 HDMI_TX1_SDA_M1 CAN2_TX_M0 UART5_RX_M1 SPI3_CS1_M3 GPIO3_C5_U |
ETH1 | Center-Tap Reference Voltage for Carrier Board Ethernet Magnetic (if required by the Module GBE PHY) | |
| S29 | PCIE_D_TX+ / SERDES_0_TX+ | PCIe3_TXP | C29 | PCIE30_PORT0_TX1P | PCIE30 | Differential PCIe link D transmit data pair | |
| S30 | PCIE_D_TX- / SERDES_0_TX- | PCIe3_TXN | B29 | PCIE30_PORT0_TX1N | PCIE30 | Differential PCIe link D transmit data pair | |
| S31 | GBE1_LINK_ACT# | ETH1_ACT_ | ETH1 | Link / Activity Indication LED Driven Low on Link (10, 100 or 1000 Mbps) Blinks on Activity | |||
| S32 | PCIE_D_RX+ / SERDES_0_RX+ | PCIe3_RXP | C31 | PCIE30_PORT0_RX1P | PCIE30 | Differential PCIe link D receive data pair | |
| S33 | PCIE_D_RX- / SERDES_0_RX- | PCIe3_RXN | B31 | PCIE30_PORT0_RX1N | PCIE30 | Differential PCIe link D receive data pair | |
| S34 | GND | PWR/GND | |||||
| S35 | USB4+ | USB4_DP | USB4 | USB | USB Differential Data Pairs for Port 4 | ||
| S36 | USB4- | USB4_DN | USB4 | USB | USB Differential Data Pairs for Port 4 | ||
| S37 | USB3_VBUS_DET | USB3_OTG_VBUS | AL8 | TYPEC1_USB20_VBUSDET | USB3 | USB Port 3 Host Power Detection. | |
| S38 | AUDIO_MCK | AUDIO_MCK | F30 | I2S0_MCLK I2C6_SDA_M1 UART3_RTSN PWM3_IR_M2 SPI4_CLK_M0 GPIO1_C2__d |
I2S1 | 1V8 | Master Clock Output to I2S Codec(s) |
| S39 | I2S0_LRCK | I2S0_LRCK | D30 | I2S0_LRCK I2C2_SCL_M3 UART4_RTSN GPIO1_C5_d |
I2S1 | 1V8 | I2S0 Left and Right Synchronization Clock |
| S40 | I2S0_SDOUT | I2S0_SDOUT | E29 | I2S0_SDO0 I2C4_SCL_M4 UART4_CTSN GPIO1_C7_d |
I2S1 | 1V8 | I2S0 Digital Audio Output |
| S41 | I2S0_SDIN | I2S0_SDIN | D28 | I2S0_SDI0 GPIO1_D4_d |
I2S1 | 1V8 | I2S0 Digital Audio Input |
| S42 | I2S0_CK | I2S0_CK_GNSS_PPS | E31 | I2S0_SCLK I2C6_SCL_M1 UART3_CTSN PWM7_IR_M2 SPI4_CS0_M0 GPIO1_C3_d |
I2S1 | 1V8 | I2S0 Digital Audio Clock |
| S43 | ESPI_ALERT0# | ESPI_ALERT0_ | L30 | SPI2_CS1_M2 I2C1_SCL_M1 UART0_RX_M1 GPIO0_B0_Z |
eSPI | PU 10K 1V8 | ESPI ALERT0 |
| S44 | ESPI_ALERT1# | ESPI_ALERT1_ | K29 | CLK32K_IN CLK32K_OUT0 GPIO0_B2__U |
eSPI | PU 10K 1V8 | ESPI ALERT1 |
| S45 | MDIO_CLK | MDIO_CLK | Y31 | GMAC1_MDC MIPI_TE0 I2C8_SCL_M4 UART7_RTSN_M1 PWM14_M0 SPI1_CS0_M1 GPIO3_C2_D |
RGMII0 | 1V8 | MDIO Signals to Configure Possible PHYs |
| S46 | MDIO_DAT | MDIO_DAT | Y30 | GMAC1_MDIO MIPI_TE1 I2C8_SDA_M4 UART7_CTSN_M1 PWM15_IR_M0 SPI1_CS1_M1 GPIO3_C3_D |
RGMII0 | 1V8 | MDIO Signals to Configure Possible PHY |
| S47 | GND | PWR/GND | |||||
| S48 | I2C_GP_CK | SMARC_I2C_GP_CK | AJ25 | BT1120_D14 PCIE20X1_2_WAKEN_M1 HDMI_TX0_SDA_M0 I2C8_SCL_M3 SPI3_CS0_M1 GPIO4_C0_U |
I2C_GP | PU 10K 1V8 | General Purpose I2C Clock Signal |
| S49 | I2C_GP_DAT | SMARC_I2C_GP_DAT | AK24 | BT1120_D15 SPDIF1_TX_M2 PCIE20X1_2_PERSTN_M1 HDMI_TX0_CEC_M0 I2C8_SDA_M3 PWM6_M1 SPI3_CS1_M1 GPIO4_C1_D |
I2C_GP | PU 10K 1V8 | General Purpose I2C Data Signal |
| S50 | HDA_SYNC / I2S2_LRCK | NC | |||||
| S51 | HDA_SDO / I2S2_SDOUT | NC | |||||
| S52 | HDA_SDI / I2S2_SDIN | NC | |||||
| S53 | HDA_CK / I2S2_CK | NC | |||||
| S54 | SATA_ACT# | SATA_ACT_ | G26 | PDM0_SDI0_M0 SPI1_,5CS1_M2 GPIO1_D5_D |
SATA | 3V3 | SATA Activity Indicator |
| S55 | USB5_EN_OC# | USB20_EN_OC_ | AG23 | CIF_D13 PCIE20X1_2_PERSTN_M0 HDMI_RX_CEC_M1 UART4_TX_M1 PWM9_M2 SPI0_MISO_M3 GPIO3_D1_D |
USB5 | PU 10k 3.3V | USB Over-Current Sense for Port 5 |
| S56 | ESPI_IO_2 / QSPI_IO_2 | NC | |||||
| S57 | ESPI_IO_3 / QSPI_IO_3 | NC | |||||
| S58 | ESPI_RESET# | ESPI_RESET_ | C25 | PDM1_SDI0_M1 PCIE30X1_1_PERSTN_M2 PWM3_IR_M3 SPI2_CS0_M0 GPIO1_A7_U |
eSPI | 1V8 | ESPI Reset |
| S59 | USB5+ | USB5_DP | USB5 | USB | USB Differential Data Pairs for Port 5 | ||
| S60 | USB5- | USB5_DN | USB5 | USB | USB Differential Data Pairs for Port 5 | ||
| S61 | GND | PWR/GND | |||||
| S62 | USB3_SSTX+ | USB3_SSTXP | AP14 | TYPEC0_SSTX1P DP0_TX1P |
USB3 | USB SS | Transmit Signal Differential Pairs for SuperSpeed on Port 3 |
| S63 | USB3_SSTX- | USB3_SSTXN | AN14 | TYPEC0_SSTX1N DP0_TX1N |
USB3 | USB SS | Transmit Signal Differential Pairs for SuperSpeed on Port 3 |
| S64 | GND | PWR/GND | |||||
| S65 | USB3_SSRX+ | USB3_SSRXP | AN13 | TYPEC0_SSRX1P DP0_TX0P |
USB3 | USB SS | Receive Signal Differential Pairs for SuperSpeed on Port 3 |
| S66 | USB3_SSRX- | USB3_SSRXN | AP13 | TYPEC0_SSRX1N DP0_TX0N |
USB3 | USB SS | Receive Signal Differential Pairs for SuperSpeed on Port 3 |
| S67 | GND | PWR/GND | |||||
| S68 | USB3+ | USB3_DP | T2 | USB3 | USB | USB Differential Data Pairs | |
| S69 | USB3- | USB3_DM | T1 | USB3 | USB | USB Differential Data Pairs | |
| S70 | GND | PWR/GND | |||||
| S71 | USB2_SSTX+ | USB2_SSTXP | AP14 | TYPEC0_SSTX1P DP0_TX1P |
USB2 | USB SS | Transmit Signal Differential Pairs for SuperSpeed on Port 2 |
| S72 | USB2_SSTX- | USB2_SSTXN | AN14 | TYPEC0_SSTX1N DP0_TX1N |
USB2 | USB SS | Transmit Signal Differential Pairs for SuperSpeed on Port 2 |
| S73 | GND | PWR/GND | |||||
| S74 | USB2_SSRX+ | USB2_SSRXP | AN13 | TYPEC0_SSRX1P DP0_TX0P |
USB2 | USB SS | Receive Signal Differential Pairs for SuperSpeed on Port 2 |
| S75 | USB2_SSRX- | USB2_SSRXN | AP13 | TYPEC0_SSRX1N DP0_TX0N |
USB2 | USB SS | Receive Signal Differential Pairs for SuperSpeed on Port 2 |
| S76 | PCIE_B_RST# | PCIe_RST_ | AG26 | CIF_D10 PCIE30X4_PERSTN_M2 HDMI_TX1_SCL_M1 SPI3_MISO_M3 GPIO3_C6_u |
PCIe1 | 3V3 | PCIe Port B reset output |
| S77 | PCIE_C_RST# | PCIe_RST_ | AG26 | CIF_D10 PCIE30X4_PERSTN_M2 HDMI_TX1_SCL_M1 SPI3_MISO_M3 GPIO3_C6_u |
PCIe2 | 3V3 | PCIe Port C reset output |
| S78 | PCIE_C_RX+ / SERDES_1_RX+ | PCIe2_RXP | B32 | PCIE30_PORT1_RX0P | PCIE2 | Differential PCIe link C receive data pair | |
| S79 | PCIE_C_RX- / SERDES_1_RX- | PCIe2_RXN | A32 | PCIE30_PORT1_RX0N | PCIE2 | Differential PCIe link C receive data pair | |
| S80 | GND | PWR/GND | |||||
| S81 | PCIE_C_TX+ / SERDES_1_TX+ | PCIe2_TXP | B30 | PCIE30_PORT1_TX0P | PCIE2 | Differential PCIe link C transmit data pair | |
| S82 | PCIE_C_TX- / SERDES_1_TX- | PCIe2_TXN | A30 | PCIE30_PORT1_TX0N | PCIE2 | Differential PCIe link C transmit data pair | |
| S83 | GND | PWR/GND | |||||
| S84 | PCIE_B_REFCK+ | PCIe1_CLKP | - | Differential PCIe Link B reference clock output | |||
| S85 | PCIE_B_REFCK- | PCIe1_CLKN | - | Differential PCIe Link B reference clock output | |||
| S86 | GND | PWR/GND | |||||
| S87 | PCIE_B_RX+ | PCIe1_RXP | F32 | PCIE30_PORT0_RX1P | PCIE3 | Differential PCIe link B receive data pair | |
| S88 | PCIE_B_RX- | PCIe1_RXN | F33 | PCIE30_PORT0_RX1N | PCIE3 | Differential PCIe link B receive data pair | |
| S89 | GND | PWR/GND | |||||
| S90 | PCIE_B_TX+ | PCIE_B_TX+ | C33 | PCIE30_PORT0_TX1P | PCIE3 | Differential PCIe link B transmit data pair | |
| S91 | PCIE_B_TX- | PCIE_B_TX- | C34 | PCIE30_PORT0_TX1N | PCIE3 | Differential PCIe link B transmit data pair | |
| S92 | GND | PWR/GND | |||||
| S93 | DP0_LANE0+ | DP0_L0+ | AJ2 | HDMI_TX0_D0P eDP_TX0_D0P |
DP0++ | Primary DP Port Differential Pair Data Lines | |
| S94 | DP0_LANE0- | DP0_L0- | AJ1 | HDMI_TX0_D0N eDP_TX0_D0N |
DP0++ | Primary DP Port Differential Pair Data Lines | |
| S95 | DP0_AUX_SEL | DP0_AUX_SEL | DP0++ | 1V8 | Auxiliary Selection | ||
| S96 | DP0_LANE1+ | DP0_L1+ | AK3 | HDMI_TX0_D1P eDP_TX0_D1P |
DP0++ | Primary DP Port Differential Pair Data Lines | |
| S97 | DP0_LANE1- | DP0_L1- | AK2 | HDMI_TX0_D1N eDP_TX0_D1N |
DP0++ | Primary DP Port Differential Pair Data Lines | |
| S98 | DP0_HPD | DP0_HPD | B26 | HDMI_TX0_HPD_M0 SPI2_MOSI_M0 GPIO1_A5_d |
DP0++ | 1V8 | DP Hot Plug Detect Input |
| S99 | DP0_LANE2+ | DP0_L2+ | AL2 | HDMI_TX0_D2P eDP_TX0_D2P |
DP0++ | Primary DP Port Differential Pair Data Lines | |
| S100 | DP0_LANE2- | DP0_L2- | AL1 | HDMI_TX0_D2N eDP_TX0_D2N |
DP0++ | Primary DP Port Differential Pair Data Lines | |
| S101 | GND | PWR/GND | |||||
| S102 | DP0_LANE3+ | DP0_L3+ | AH3 | HDMI_TX0_D3P eDP_TX0_D3P |
DP0++ | Primary DP Port Differential Pair Data Lines | |
| S103 | DP0_LANE3- | DP0_L3- | AH2 | HDMI_TX0_D3N eDP_TX0_D3N |
DP0++ | Primary DP Port Differential Pair Data Lines | |
| S104 | USB3_OTG_ID | USB3_OTG_ID | AK8 | TYPEC1_USB20_OTG_ID | USB3 | 3V3 | Input Pin to Announce OTG Device Insertion on USB 2.0 Port |
| S105 | DP0_AUX+ | DP0_AUX+ | AG2 | HDMI_TX0_SBDP eDP_TX0_AUXP |
DP0++ | 3V3 | Primary DP Port Bidirectional Channel used for Link Management and Device Control |
| S106 | DP0_AUX- | DP0_AUX- | AG1 | HDMI_TX0_SBDN eDP_TX0_AUXN |
DP0++ | 3V3 | Primary DP Port Bidirectional Channel used for Link Management and Device Control |
| S107 | LCD1_BKLT_EN | LCD_BKLT_EN | eDP1 | 1V8 | Secondary LVDS Channel Backlight Enable | ||
| S108 | LVDS1_CK+ / eDP1_AUX+ / DSI1_CLK+ | DSI1_CLKP | AN20 | MIPI_DPHY1_TX_CLKP MIPI_CPHY1_TX_TRIO1_C |
DSI1 | Secondary DSI Panel Differential Pair Clock Lines | |
| S109 | LVDS1_CK- / eDP1_AUX- / DSI1_CLK- | DSI1_CLKN | AP20 | MIPI_DPHY1_TX_CLKN MIPI_CPHY1_TX_TRIO1_B |
DSI1 | Secondary DSI Panel Differential Pair Clock Lines | |
| S110 | GND | PWR/GND | |||||
| S111 | LVDS1_0+ / eDP1_TX0+ / DSI1_D0+ | DSI1_D0P | AN18 | MIPI_DPHY1_TX_D0P MIPI_CPHY1_TX_TRIO0_B |
DSI1 | Secondary DSI Panel Differential Pair Data Lines 0 | |
| S112 | LVDS1_0- / eDP1_TX0- / DSI1_D0- | DSI1_D0N | AP18 | MIPI_DPHY1_TX_D0N MIPI_CPHY1_TX_TRIO0_A |
DSI1 | Secondary DSI Panel Differential Pair Data Lines 0 | |
| S113 | eDP1_HPD / DSI1_TE | DSI1_TE | DSI1 | 1V8 | Detection of Hot Plug / Unplug of Secondary eDP Display and Notification of the Link Layer | ||
| S114 | LVDS1_1+ / eDP1_TX1+ / DSI1_D1+ | DSI1_D1P | AN19 | MIPI_DPHY1_TX_D1P MIPI_CPHY1_TX_TRIO1_A |
DSI1 | Secondary DSI Panel Differential Pair Data Lines 1 | |
| S115 | LVDS1_1- / eDP1_TX1- / DSI1_D1- | DSI1_D1N | AP19 | MIPI_DPHY1_TX_D1N MIPI_CPHY1_TX_TRIO0_C |
DSI1 | Secondary DSI Panel Differential Pair Data Lines 1 | |
| S116 | LCD1_VDD_EN | LCD_VDD_EN | DSI1 | 1V8 | Secondary Panel Power Enable | ||
| S117 | LVDS1_2+ / eDP1_TX2+ / DSI1_D2+ | DSI1_D2P | AN21 | MIPI_DPHY1_TX_D2P MIPI_CPHY1_TX_TRIO2_B |
DSI1 | Secondary DSI Panel Differential Pair Data Lines 2 | |
| S118 | LVDS1_2- / eDP1_TX2- / DSI1_D2- | DSI1_D2N | AP21 | MIPI_DPHY1_TX_D2N MIPI_CPHY1_TX_TRIO2_A |
DSI1 | Secondary DSI Panel Differential Pair Data Lines 2 | |
| S119 | GND | PWR/GND | |||||
| S120 | LVDS1_3+ / eDP1_TX3+ / DSI1_D3+ | DSI1_D3P | AN22 | MIPI_DPHY1_TX_D3P NO_USE |
DSI1 | Secondary DSI Panel Differential Pair Data Lines 3 | |
| S121 | LVDS1_3- / eDP1_TX3- / DSI1_D3- | DSI1_D3N | AP22 | MIPI_DPHY1_TX_D3N MIPI_CPHY1_TX_TRIO2_C |
DSI1 | Secondary DSI Panel Differential Pair Data Lines 3 | |
| S122 | LCD1_BKLT_PWM | LCD_PWM | AE31 | GMAC0_RXDV_CRS UART7_RTSN_M0 PWM2_M2 SPI3_CS0_M0 GPIO4_C2_d |
1V8 | DSI1 | Secondary Panel Brightness Control |
| S123 | GPIO13 | GPIO13 | GPIO | 1V8 | GPIO Pin 13 Preferred Output | ||
| S124 | GND | PWR/GND | |||||
| S125 | LVDS0_0+ / eDP0_TX0+ / DSI0_D0+ | DSI0_D0P | AP24 | MIPI_DPHY0_TX_D0P MIPI_CPHY0_TX_TRIO0_B |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S126 | LVDS0_0- / eDP0_TX0- / DSI0_D0- | DSI0_D0N | AN25 | MIPI_DPHY0_TX_D0N MIPI_CPHY0_TX_TRIO0_A |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S127 | LCD0_BKLT_EN | LCD0_BKLT_EN | DSI0 | 1V8 | Primary Panel Backlight Enable | ||
| S128 | LVDS0_1+ / eDP0_TX1+ / DSI0_D1+ | DSI0_D1P | AN25 | MIPI_DPHY0_TX_D1P MIPI_CPHY0_TX_TRIO1_A |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S129 | LVDS0_1- / eDP0_TX1- / DSI0_D1- | DSI0_D1N | AP25 | MIPI_DPHY0_TX_D1N MIPI_CPHY0_TX_TRIO0_C |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S130 | GND | PWR/GND | |||||
| S131 | LVDS0_2+ / eDP0_TX2+ / DSI0_D2+ | DSI0_D2P | AN27 | MIPI_DPHY0_TX_D2P MIPI_CPHY0_TX_TRIO2_B |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S132 | LVDS0_2- / eDP0_TX2- / DSI0_D2- | DSI0_D2N | AP27 | MIPI_DPHY0_TX_D2N MIPI_CPHY0_TX_TRIO2_A |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S133 | LCD0_VDD_EN | LCD_VDD_EN | DSI0 | 1V8 | Primary Panel Power Enable | ||
| S134 | LVDS0_CK+ / eDP0_AUX+ / DSI0_CLK+ | DSI0 _CLKP | AN26 | MIPI_DPHY0_TX_CLKP MIPI_CPHY0_TX_TRIO1_C |
DSI0 | Primary DSI Panel Differential Pair Clock Lines | |
| S135 | LVDS0_CK- / eDP0_AUX- / DSI0_CLK- | DSI0 _CLKN | AP26 | MIPI_DPHY0_TX_CLKN MIPI_CPHY0_TX_TRIO1_B |
DSI0 | Primary DSI Panel Differential Pair Clock Lines | |
| S136 | GND | PWR/GND | |||||
| S137 | LVDS0_3+ / eDP0_TX3+ / DSI0_D3+ | DSI0_D3P | AN28 | MIPI_DPHY0_TX_D3P NO_USE |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S138 | LVDS0_3- / eDP0_TX3- / DSI0_D3- | DSI0_D3N | AP28 | MIPI_DPHY0_TX_D3N MIPI_CPHY0_TX_TRIO2_C |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S139 | I2C_LCD_CK | I2C_LCD_CK | W31 | I2S1_SDI3_M1 PDM0_SDI1_M1 I2C6_SCL_M0 UART1_CTSN_M2 PWM7_IR_M0 SPI3_MISO_M2 PCIE30X4_PERSTN_M0 GPIO0_D0_D |
DSI | PU 2.2K 1V8 | I2C clock to read LCD display EDID EEPROMs |
| S140 | I2C_LCD_DAT | I2C_LCD_DAT | V31 | I2S1_SDI2_M1 PDM0_SDI0_M1 I2C6_SDA_M0 UART1_RTSN_M2 PWM6_M0 SPI0_MISO_M0 PCIE30X4_WAKEN_M0 GPIO0_C7_D |
DSI | PU 2.2K 1V8 | DDC Data Line Used for Flat Panel Detection and Control |
| S141 | LCD0_BKLT_PWM | LCD0_BKLT_PWM | AE31 | GMAC0_RXDV_CRS UART7_RTSN_M0 PWM2_M2 SPI3_CS0_M0 GPIO4_C2_d |
DSI0 | 1V8 | Primary Panel Brightness Control |
| S142 | GPIO12 | GPIO12 | GPIO | 1V8 | GPIO Pin 12 Preferred Output | ||
| S143 | GND | PWR/GND | |||||
| S144 | eDP0_HPD / DSI0_TE | DSI0_TE | DSI0 | 1V8 | Primary DSI Panel Tearing Effect Signal | ||
| S145 | WDT_TIME_OUT# | WDT_TIME_OUT_ | - | WATCHDOG | 1V8 | Watch-Dog-Timer Output, low active | |
| S146 | PCIE_WAKE# | PCIe_WAKE_ | AG25 | CIF_D14 PCIE30X2_CLKREQN_M2 HDMI_RX_SCL_M1 I2C7_SCL_M2 UART9_RTSN_M2 SPI0_MOSI_M3 GPIO3_D2_d |
PCIE | 3V3 | PCIe wake up interrupt to host – common to PCIe links A, B, C, D |
| S147 | VDD_RTC | VDD_RTC | PWR RTC | ||||
| S148 | LID# | LID_ | - | MANAGEMENT | PU 1.8K 1V8 | Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in inactive state. Active low, level sensitive. Should be de-bounced on the Module. | |
| S149 | SLEEP# | SLEEP_ | - | MANAGEMENT | PU 1.8K 1V8 | Sleep indicator from Carrier Board. May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module. | |
| S150 | VIN_PWR_BAD# | X_VIN_PWR_BAD_ | - | MANAGEMENT | PU 10K 5V | Power bad indication from Carrier Board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall not be enabled while this signal is held low by the Carrier. | |
| S151 | CHARGING# | CHARGING_ | MANAGEMENT | PU 10K 1V8 | Held low by Carrier during battery charging. Carrier to float the line when charge is complete. | ||
| S152 | CHARGER_PRSNT# | CHARGER_PRSNT_ | MANAGEMENT | PU 10K 1V8 | Held low by Carrier if DC input for battery charger is present | ||
| S153 | CARRIER_STBY# | CARRIER_STBY_ | - | MANAGEMENT | 1V8 | The Module shall drive this signal low when the system is in a standby power state. | |
| S154 | CARRIER_PWR_ON | CARRIER_PWR_ON | - | MANAGEMENT | 1V8 | Carrier Board circuits (apart from power management and power path circuits) should not be powered up until the Module asserts the CARRIER_PWR_ON signal. | |
| S155 | FORCE_RECOV# | FORCE_RECOVER_ | BOOT | PU 10K 1V8 | Low on this pin allows nonprotected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode – such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier. | ||
| S156 | BATLOW# | BATLOW_ | - | MANAGEMENT | PU 10K 1V8 | Battery low indication to Module. Carrier to float the line in inactive state | |
| S157 | TEST# | TEST_ | - | MANAGEMENT | PU 10K 1V8 | Held Low by Carrier to Invoke Module Vendor Specific Test Functions | |
| S158 | GND | PWR/GND |