| Pin # | SMARC Pin Name | Board Signal | CPU Pin | CPU Functions | Group | I/O Level | Comments |
|---|---|---|---|---|---|---|---|
| P1 | SMB_ALERT# | SMB_ALERT_ | AD23 | CLK32K_IN CLK32K_OUT0 PCIE30X2_BUTTONRSTN GPIO0_B0_U |
MANAGEMENT | PU 1.8V | SMBus Alert# (Interrupt) Signal |
| P2 | GND | PWR/GND | |||||
| P3 | CSI1_CK+ | CSI1_CLKP | AG10 | MIPI_CSI_RX_CLK0P | CSI1 | CSI1 differential clock input (point to point) | |
| P4 | CSI1_CK- | CSI1_CLKN | AH10 | MIPI_CSI_RX_CLK0N | CSI1 | CSI1 differential clock input (point to point) | |
| P5 | GBE1_SDP | NC | |||||
| P6 | GBE0_SDP | NC | |||||
| P7 | CSI1_RX0+ | CSI1_D0P | AG12 | MIPI_CSI_RX_D0P | CSI1 | CSI1 differential input (point to point) | |
| P8 | CSI1_RX0- | CSI1_D0N | AH12 | MIPI_CSI_RX_D0N | CSI1 | CSI1 differential input (point to point) | |
| P9 | GND | PWR/GND | |||||
| P10 | CSI1_RX1+ | CSI1_D1P | AG11 | MIPI_CSI_RX_D1P | CSI1 | CSI1 differential input (point to point) | |
| P11 | CSI1_RX1- | CSI1_D1N | AH11 | MIPI_CSI_RX_D1N | CSI1 | CSI1 differential input (point to point) | |
| P12 | GND | PWR/GND | |||||
| P13 | CSI1_RX2+ | CSI1_D2P | AE11 | MIPI_CSI_RX_D2P | CSI1 | CSI1 differential input (point to point) | |
| P14 | CSI1_RX2- | CSI1_D2N | AD11 | MIPI_CSI_RX_D2N | CSI1 | CSI1 differential input (point to point) | |
| P15 | GND | PWR/GND | |||||
| P16 | CSI1_RX3+ | CSI1_D3P | *) | ||||
| P17 | CSI1_RX3- | CSI1_D3N | *) | ||||
| P18 | GND | PWR/GND | |||||
| P19 | GBE0_MDI3- | ETH0_TX3N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P20 | GBE0_MDI3+ | ETH0_TX3P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P21 | GBE0_LINK100# | ETH0_LINK10/100_ | - | GBE0 | 3V3 | Link Speed Indication LED for GBE0 100Mbps | |
| P22 | GBE0_LINK1000# | ETH0_LINK1000_ | - | GBE0 | 3V3 | Link Speed Indication LED for GBE0 1000Mbps | |
| P23 | GBE0_MDI2- | ETH0_TX2N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P24 | GBE0_MDI2+ | ETH0_TX2P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P25 | GBE0_LINK_ACT# | ETH0_ACT_ | - | GBE0 | 3V3 | Link / Activity Indication LED Driven Low on Link (10, 100 or 1000 Mbps) Blinks on Activity | |
| P26 | GBE0_MDI1- | ETH0_TX1N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P27 | GBE0_MDI1+ | ETH0_TX1P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P28 | GBE0_CTREF | - | - | GBE0 | 0…3V3 | Center-Tap Reference Voltage for Carrier Board Ethernet Magnetic (if required by the Module GBE PHY) | |
| P29 | GBE0_MDI0- | ETH0_TX0N | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P30 | GBE0_MDI0+ | ETH0_TX0P | - | GBE0 | Differential Pair Signals for External Transformer | ||
| P31 | SPI0_CS1# | SPI2_CS1_ | AF5 | SPI2_CS1_M1 PCIE30X2_CLKREQN_M1 I2S1_SDI1_M2 LCDC_D4 VOP_BT656_D4_M0 GPIO2_D4_D |
SPI2 | 1V8 | SPI2 Master Chip Select 1 |
| P32 | GND | PWR/GND | |||||
| P33 | SDIO_WP | SDMMC0_WP | AE24 | GPU_PWREN SATA_CP_POD PCIE30X2_CLKREQN_M0 GPIO0_A6_D |
SDIO | 1V8 or 3V3 | SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards. |
| P34 | SDIO_CMD | SDMMC0_CMD | H27 | SDMMC0_CMD PWM10_M1 UART5_RX_M0 CAN0_TX_M1 GPIO2_A1_U |
SDIO | 1V8 or 3V3 | SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode. |
| P35 | SDIO_CD# | SDMMC0_DET_ | Y22 | SDMMC0_DET SATA_CP_DET PCIE30X1_CLKREQN_M0 GPIO0_A4_U |
SDIO | 1V8 or 3V3 | SDIO Card Detect. This signal indicates when a SDIO/MMC card is present. |
| P36 | SDIO_CK | SDMMC0_CLK | H28 | SDMMC0_CLK TEST_CLKOUT UART5_TX_M0 CAN0_RX_M1 GPIO2_A2_D |
SDIO | 1V8 or 3V3 | SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. |
| P37 | SDIO_PWR_EN | SDMMC0_PWR_EN | - | SDIO | 3V3 | DIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device. | |
| P38 | GND | PWR/GND | |||||
| P39 | SDIO_D0 | SDMMC0_D0 | J25 | SDMMC0_D0 UART2_TX_M1 UART6_TX_M1 PWM8_M1 GPIO1_D5_U |
SDIO | 1V8 or 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P40 | SDIO_D1 | SDMMC0_D1 | J24 | SDMMC0_D1 UART2_RX_M1 UART6_RX_M1 PWM9_M1 GPIO1_D6_U |
SDIO | 1V8 or 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P41 | SDIO_D2 | SDMMC0_D2 | H26 | SDMMC0_D2 ARMJTAG_TCK UART5_CTSN_M0 GPIO1_D7_U |
SDIO | 1V8 or 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P42 | SDIO_D3 | SDMMC0_D3 | J23 | SDMMC0_D3 ARMJTAG_TMS UART5_RTSN_M0 GPIO2_A0_U |
SDIO | 1V8 or 3V3 | SDIO Data lines. These signals operate in push-pull mode. |
| P43 | SPI0_CS0# | SPI2_CS0_ | AF6 | SPI2_CS0_M1 PCIE30X2_WAKEN_M1 I2S1_SDI2_M2 LCDC_D5 VOP_BT656_D5_M0 GPIO2_D5_D |
SPI2 | 1V8 | SPI2 Master Chip Select 0 |
| P44 | SPI0_CK | SPI2_SCLK | AH4 | SPI2_CLK_M1 UART8_RX_M1 I2S1_SDO1_M2 LCDC_CLK VOP_BT656_CLK_M0 GPIO3_A0_D |
SPI2 | 1V8 | SPI2 Clock |
| P45 | SPI0_DIN | SPI2_MISO | AH5 | SPI2_MISO_M1 UART8_TX_M1 I2S1_SDO0_M2 LCDC_D7 VOP_BT656_D7_M0 GPIO2_D7_D |
SPI2 | 1V8 | SPI2 Master input / Slave output |
| P46 | SPI0_DO | SPI2_MOSI | AD6 | SPI2_MOSI_M1 PCIE30X2_PERSTN_M1 I2S1_SDI3_M2/LCDC_D6 VOP_BT656_D6_M0 GPIO2_D6_D |
SPI2 | 1V8 | SPI2 Master output / Slave input |
| P47 | GND | PWR/GND | |||||
| P48 | SATA_TX+ | SATA_TXP | - | SATA MUX USB3.0 |
SATA | Serial ATA Channel 0 Transmit Output Differential Pair | |
| P49 | SATA_TX- | SATA_TXN | - | SATA MUX USB3.0 |
SATA | Serial ATA Channel 0 Transmit Output Differential Pair | |
| P50 | GND | PWR/GND | |||||
| P51 | SATA_RX+ | SATA_RXP | - | SATA MUX USB3.0 |
SATA | Serial ATA Channel 0 Receive Input Differential Pair | |
| P52 | SATA_RX- | SATA_RXN | - | SATA MUX USB3.0 |
SATA | Serial ATA Channel 0 Receive Input Differential Pair | |
| P53 | GND | PWR/GND | |||||
| P54 | ESPI_CS0# / SPI1_CS0# / QSPI_CS0# | X1_QSPI_CS0_ | *) | ||||
| P55 | ESPI_CS1# / SPI1_CS1# / QSPI_CS1# | X1_QSPI_CS1_ | *) | ||||
| P56 | ESPI_CK / SPI1_CK / QSPI_CK | X1_QSPI_SCLK | *) | ||||
| P57 | ESPI_IO_1 / SPI1_DIN / QSPI_IO_1 | X1_QSPI_D1 | *) | ||||
| P58 | ESPI_IO_0 / SPI1_DO / QSPI_IO_0 | X1_QSPI_D0 | *) | ||||
| P59 | GND | PWR/GND | |||||
| P60 | USB0+ | USB_OTG_DP | P27 | USB3_OTG0_DP | USB3 | USB | USB Differential Data Pairs for Port 3 |
| P61 | USB0- | USB3_OTG0_DM | P28 | USB3_OTG0_DM | USB3 | USB | USB Differential Data Pairs for Port 3 |
| P62 | USB0_EN_OC# | USB0_OC_ | AF25 | SDMMC0_PWREN SATA_MP_SWITCH PCIE20_CLKREQN_M0 GPIO0_A5_D |
USB0 | 3V3 | USB Over-Current Sense for Port 0 |
| P63 | USB0_VBUS_DET | USB_OTG_VBUS | M24 | USB3_OTG0_VBUSDET | USB3 | 5V | USB Port 3 Host Power Detection |
| P64 | USB0_OTG_ID | USB_OTG_ID | L23 | USB3_OTG0_ID | USB3 | PU 10k 1.8V | |
| P65 | USB1+ | USB_H2_DP | R2 | USB2_HOST2_DP | USB2 | USB | USB Differential Data Pairs for Port 2 |
| P66 | USB1- | USB_H2_DM | R1 | USB2_HOST2_DM | USB2 | USB | USB Differential Data Pairs for Port 2 |
| P67 | USB1_EN_OC# | USB1_OC_ | AF25 | SDMMC0_PWREN SATA_MP_SWITCH PCIE20_CLKREQN_M0 GPIO0_A5_D |
USB1 | PU 3.3V 10k | USB Over-Current Sense for Port 1 |
| P68 | GND | PWR/GND | |||||
| P69 | USB2+ | USB_H1_DP | P24 | USB3_HOST1_DP | USB3 | USB | USB Differential Data Pairs for Port 3 |
| P70 | USB2- | USB_H1_DM | P25 | USB3_HOST1_DM | USB3 | USB | USB Differential Data Pairs for Port 3 |
| P71 | USB2_EN_OC# | USB2_OC_ | AF25 | SDMMC0_PWREN SATA_MP_SWITCH PCIE20_CLKREQN_M0 GPIO0_A5_D |
USB2 | PU 3.3V 10k | USB Over-Current Sense for Port 2 |
| P72 | RSVD | X1_ADC_IN5 | - | SARADC_VIN5 | RSVD | ||
| P73 | RSVD | X1_ADC_IN6 | - | SARADC_VIN6 | RSVD | ||
| P74 | USB3_EN_OC# | USB3_OC_ | AF25 | SDMMC0_PWREN SATA_MP_SWITCH PCIE20_CLKREQN_M0 GPIO0_A5_D |
USB3 | PU 3.3V 10k | USB Over-Current Sense for Port 3 |
| P75 | PCIE_A_RST# | PCIe0_RST_ | AD20 | PWM7_IR SPI0_CS0_M0 GPIO0_C6_D |
PCIe0 | 3V3 | PCIe Port A reset output |
| P76 | USB4_EN_OC# | NC | - | ||||
| P77 | PCIE_B_CKREQ# | PCIe1_CLKREQ_ | - | PCIe1 | PCIe Port B clock request | ||
| P78 | PCIE_A_CKREQ# | PCIe0_CLKREQ_ | - | PCIe0 | PCIe Port A clock request | ||
| P79 | GND | PWR/GND | |||||
| P80 | PCIE_C_REFCK+ | PCIE20_CLKP | - | PCIE20_REFCLKP | PCIE20 | Differential PCIe Link C reference clock output | |
| P81 | PCIE_C_REFCK- | PCIE20_CLKN | - | PCIE20_REFCLKN | PCIE20 | Differential PCIe Link C reference clock output | |
| P82 | GND | PWR/GND | |||||
| P83 | PCIE_A_REFCK+ | PCIe0_CLKP | - | PCIe0_CLKP | PCIe0 | Differential PCIe Link A reference clock output | |
| P84 | PCIE_A_REFCK- | PCIe0_CLKN | - | PCIe0_CLKN | PCIe0 | Differential PCIe Link A reference clock output | |
| P85 | GND | PWR/GND | |||||
| P86 | PCIE_A_RX+ | PCIE30_RX0P | AC28 | PCIE30_RX0P | PCIE30 | Differential PCIe link A receive data pair | |
| P87 | PCIE_A_RX- | PCIE30_RX0N | AC27 | PCIE30_RX0N | PCIE30 | Differential PCIe link A receive data pair | |
| P88 | GND | PWR/GND | |||||
| P89 | PCIE_A_TX+ | PCIE30_TX0P | AA28 | PCIE30_TX0P | PCIE30 | Differential PCIe link A transmit data pair | |
| P90 | PCIE_A_TX- | PCIE30_TX0N | AA27 | PCIE30_TX0N | PCIE30 | Differential PCIe link A transmit data pair | |
| P91 | GND | PWR/GND | |||||
| P92 | HDMI_D2+ / DP1_LANE0+ | HDMI_D2P | AG22 | HDMI_TX_D2P | HDMI | HDMI Port, Differential Pair Data Lines | |
| P93 | HDMI_D2- / DP1_LANE0- | HDMI_D2N | AH22 | HDMI_TX_D2N | HDMI | HDMI Port, Differential Pair Data Lines | |
| P94 | GND | PWR/GND | |||||
| P95 | HDMI_D1+ / DP1_LANE1+ | HDMI_D1P | AG21 | HDMI_TX_D1P | HDMI | HDMI Port, Differential Pair Data Lines | |
| P96 | HDMI_D1- / DP1_LANE1- | HDMI_TX_D1N | AH21 | HDMI_TX_D1N | HDMI | HDMI Port, Differential Pair Data Lines | |
| P97 | GND | PWR/GND | |||||
| P98 | HDMI_D0+ / DP1_LANE2+ | HDMI_D0P | AG20 | HDMI_TX_D0P | HDMI | HDMI Port, Differential Pair Data Lines | |
| P99 | HDMI_D0- / DP1_LANE2- | HDMI_D0N | AH20 | HDMI_TX_D0N | HDMI | HDMI Port, Differential Pair Data Lines | |
| P100 | GND | PWR/GND | |||||
| P101 | HDMI_CK+ / DP1_LANE3+ | HDMI_CLKP | AH19 | HDMI_TX_CLKP | HDMI | HDMI Port, Differential Pair Clock Lines | |
| P102 | HDMI_CK- / DP1_LANE3- | HDMI_CLKN | AG19 | HDMI_TX_CLKN | HDMI | HDMI Port, Differential Pair Clock Lines | |
| P103 | GND | PWR/GND | |||||
| P104 | HDMI_HPD / DP1_HPD | HDMI_HPD | AB18 | HDMI_TX_HPDIN | HDMI | PD 1V8 | HDMI Hot Plug Active High Detection Signal that Serves as an Interrupt Request |
| P105 | HDMI_CTRL_CK / DP1_AUX+ | HDMI_SCL | AG8 | HDMITX_SCL I2C5_SCL_M1 GPIO4_C7_U |
HDMI | PU 1V8 | I2C_CLK Line Dedicated to HDMI |
| P106 | HDMI_CTRL_DAT / DP1_AUX- | HDMI_SDA | AG7 | HDMITX_SDA I2C5_SDA_M1 GPIO4_D0_U |
HDMI | PU 1V8 | I2C_DAT Line Dedicated to HDMI |
| P107 | DP1_AUX_SEL | DP1_AUX_SEL | AE26 | GPIO0_D3_D | DP1++_HDMI | 1V8 | Strapping Signal to Enable Either HDMI or DP Output |
| P108 | GPIO0 / CAM0_PWR# | GPIO0_SPI0_CLK | AC7 | SPI0_CLK_M1 PCIE30X1_WAKEN_M1 I2S1_SDI0_M2 LCDC_D3 VOP_BT656_D3_M0 GPIO2_D3_D |
GPIO | 1V8 | GPIO Pin 0 Preferred Output |
| P109 | GPIO1 / CAM1_PWR# | GPIO1_SPI0_MISO | AG6 | SPI0_MISO_M1 PCIE20_CLKREQN_M1 I2S1_MCLK_M2 LCDC_D0 VOP_BT656_D0_M0 GPIO2_D0_D |
GPIO | 1V8 | GPIO Pin 1 Preferred Output |
| P110 | GPIO2 / CAM0_RST# | GPIO2_SPI0_MOSI | AD7 | SPI0_MOSI_M1 PCIE20_WAKEN_M1 I2S1_SCLK_TX_M2 LCDC_D1 VOP_BT656_D1_M0 GPIO2_D1_D |
GPIO | 1V8 | GPIO Pin 2 Preferred Output |
| P111 | GPIO3 / CAM1_RST# | GPIO3_SPI0_CS_ | AC8 | SPI0_CS0_M1 PCIE30X1_CLKREQN_M1 I2S1_LRCK_TX_M2 LCDC_D2 VOP_BT656_D2_M0 GPIO2_D2_D |
GPIO | 1V8 | GPIO Pin 3 Preferred Output |
| P112 | GPIO4 / HDA_RST# | GPIO4_SPI3_CS_ | AE8 | PWM13_M1 SPI3_CS0_M1 SATA0_ACT_LED UART9_RX_M1 I2S3_SDI_M1 GPIO4_C6_D |
GPIO | 1V8 | GPIO Pin 4 Preferred Output |
| P113 | GPIO5 / PWM_OUT | GPIO5_SPI3_CLK_PWM | AF8 | PWM14_M1 SPI3_CLK_M1 CAN1_RX_M1 PCIE30X2_CLKREQN_M2 I2S3_MCLK_M1 GPIO4_C2_D |
GPIO | 1V8 | GPIO Pin 5 Preferred Output |
| P114 | GPIO6 / TACHIN | GPIO6_SPI3_MISO | AD8 | PWM12_M1 SPI3_MISO_M1 SATA1_ACT_LED UART9_TX_M1 I2S3_SDO_M1 GPIO4_C5_D |
GPIO | 1V8 | GPIO Pin 6 Preferred Output |
| P115 | GPIO7 | GPIO7_SPI3_MOSI | AA11 | PWM15_IR_M1 SPI3_MOSI_M1 CAN1_TX_M1 PCIE30X2_WAKEN_M2 I2S3_SCLK_M1 GPIO4_C3_D |
GPIO | 1V8 | GPIO Pin 7 Preferred Output |
| P116 | GPIO8 | GPIO8_SPI1_CLK | AC4 | SPI1_CLK_M1 UART5_RX_M1 I2S1_SCLK_RX_M2 LCDC_DEN VOP_BT1120_D15 GPIO3_C3_D |
GPIO | 1V8 | GPIO Pin 8 Preferred Output |
| P117 | GPIO9 | GPIO9_SPI1_MISO | AA7 | SPI1_MISO_M1 UART5_TX_M1 I2S1_SDO3_M2 LCDC_VSYNC VOP_BT1120_D14 GPIO3_C2_D |
GPIO | 1V8 | GPIO Pin 9 Preferred Output |
| P118 | GPIO10 | GPIO10_SPI1_MOSI | AD1 | SPI1_MOSI_M1 PCIE20_PERSTN_M1 I2S1_SDO2_M2 LCDC_HSYNC VOP_BT1120_D13 GPIO3_C1_D |
GPIO | 1V8 | GPIO Pin 10 Preferred Output |
| P119 | GPIO11 | GPIO11_SPI1_CS_ | AB8 | SPI1_CS0_M1 PCIE30X1_PERSTN_M1 SDMMC2_D0_M1 LCDC_D8 VOP_BT1120_D0 GPIO3_A1_D |
GPIO | 1V8 | GPIO Pin 11 Preferred Output |
| P120 | GND | PWR/GND | |||||
| P121 | I2C_PM_CK | I2C0_SCL | AF24 | I2C0_SCL GPIO_B1_U |
MANAGEMENT | PU 2.2K 1V8 | Power management I2C bus CLK |
| P122 | I2C_PM_DAT | I2C0_SDA | AB21 | I2C0_SDA GPIO_B2_U |
MANAGEMENT | PU 2.2K 1V8 | Power management I2C bus DATA |
| P123 | BOOT_SEL0# | X1_BOOT_SEL0_ | - | BOOT | PU 10K 1V8 | Input straps determine the Module boot device | |
| P124 | BOOT_SEL1# | X1_BOOT_SEL1_ | - | BOOT | PU 10K 1V8 | Input straps determine the Module boot device | |
| P125 | BOOT_SEL2# | X1_BOOT_SEL2_ | - | BOOT | PU 10K 1V8 | Input straps determine the Module boot device | |
| P126 | RESET_OUT# | X1_RESET_OUT_ | - | MANAGEMENT | PU 10K 1V8 | General purpose reset output to Carrier Board | |
| P127 | RESET_IN# | X1_RESET_IN_ | - | MANAGEMENT | PU 10K 1V8 | Reset input from Carrier Board. Carrier drives low to force a Module reset, floats the line otherwise. This signal Shall be level triggered during bootup to allow to stop booting of the module. After bootup it May act as an edge triggered signal | |
| P128 | POWER_BTN# | X1_POWER_BTN_ | - | MANAGEMENT | PU 10K 1V8 | Power-button input from Carrier Board. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module. | |
| P129 | SER0_TX | UART0_TX | AF23 | PWM2_M0 NPUAVS UART0_TX MCU_JTAG_TDI GPIO0_C1_D |
UART0 | 1V8 | Asynchronous Serial Data Output Port 0 |
| P130 | SER0_RX | UART0_RX | AD22 | PWM1_M0 GPUAVS UART0_RX GPIO0_C0_D |
UART0 | 1V8 | Asynchronous Serial Data Input Port 0 |
| P131 | SER0_RTS# | UART0_RTS | AD21 | PWM5 SPI0_CS1_M0 UART0_RTSN GPIO0_C4_D |
UART0 | 1V8 | Request to Send Handshake Line for Port 0 |
| P132 | SER0_CTS# | UART0_CTS | AH25 | HDMITX_CEC_M1 PWM0_M1 UART0_CTSN GPIO0_C7_D |
UART0 | 1V8 | Clear to Send Handshake Line for Port 0 |
| P133 | GND | PWR/GND | |||||
| P134 | SER1_TX | SER1_TX | AH24 | UART2_TX_M0 GPIO0_D1_U |
SER1 | 1V8 | Asynchronous Serial Data Output Port 1 |
| P135 | SER1_RX | SER1_RX | AC20 | UART2_RX_M0 GPIO0_D0_U |
SER1 | 1V8 | Asynchronous Serial Data Input Port 1 |
| P136 | SER2_TX | X1_UART1_TX | Y6 | GMAC1_TXD2_M1 UART1_TX_M1 PDM_CLK0_M1 CIF_D8 EBC_SDDO8 GPIO3_D6_D |
SER2 | 1V8 | Asynchronous Serial Data Output Port 2 |
| P137 | SER2_RX | X1_UART1_RX | Y5 | GMAC1_TXD3_M1 UART1_RX_M1 PDM_SDI0_M1 CIF_D9 EBC_SDDO9 GPIO3_D7_D |
SER2 | 1V8 | Asynchronous Serial Data Input Port 2 |
| P138 | SER2_RTS# | X1_UART1_RTS | U5 | GMAC1_MDC_M1 UART1_RTSN_M1 I2S2_MCLK_M1 CIF_HREF EBC_SDLE GPIO4_B6_D |
SER2 | 1V8 | Request to Send Handshake Line for Port 2 |
| P139 | SER2_CTS# | X1_UART1_CTS | U2 | GMAC1_MCLKINOUT_M1 UART1_CTSN_M1 I2S2_SCLK_RX_M1 CIF_CLKIN EBC_SDCLK GPIO4_C1_D |
SER2 | 1V8 | Clear to Send Handshake Line for Port 2 |
| P140 | SER3_TX | UART4_TX | C20 | I2S1_LRCK_RX_M0 UART4_TX_M0 PDM_CLK0_M0 AUDIOPWM_ROUT_P GPIO1_A6_D |
SER3 | 1V8 | Asynchronous Serial Data Output Port 3 |
| P141 | SER3_RX | UART4_RX | F18 | I2S1_SCLK_RX_M0 UART4_RX_M0 PDM_CLK1_M0 SPDIF_TX_M0 GPIO1_A4_D |
SER3 | 1V8 | Asynchronous Serial Data Input Port 3 |
| P142 | GND | PWR/GND | |||||
| P143 | CAN0_TX | CAN1_TX | V5 | I2C2_SCL_M1 CAN2_TX_M0 I2S1_SDO3_M1 EBC_SDSHR GPIO4_B5_D |
CAN1 | 1V8 | CAN Port 1 Transmit Output |
| P144 | CAN0_RX | CAN1_RX | V6 | I2C2_SDA_M1 CAN2_RX_M0 ISP_FLASH_TRIGIN VOP_BT656_CLK_M1 EBC_GDSP GPIO4_B4_D |
CAN1 | 1V8 | CAN Port 1 Receive Input |
| P145 | CAN1_TX | *) | |||||
| P146 | CAN1_RX | *) | |||||
| P147 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P148 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P149 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P150 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P151 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P152 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P153 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P154 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P155 | VDD_IN | +5V_SYS | PWR | 5V | |||
| P156 | VDD_IN | +5V_SYS | PWR | 5V | |||
| S1 | CSI1_TX+ / I2C_CAM1_CK | CSI1_I2C_SCL | AC22 | I2C2_SCL_M0 SPI0_CLK_M0 PCIE20_WAKEN_M0 PWM1_M1 GPIO0_B5_U |
CSI1 | PU 2.2K 1V8 | I2C clock for serial camera data support link or differential data lane |
| S2 | CSI1_TX- / I2C_CAM1_DAT | CSI1_I2C_SDA | AA20 | I2C2_SDA_M0 SPI0_MOSI_M0 PCIE20_PERSTN_M0 PWM2_M1 GPIO0_B6_U |
CSI1 | PU 2.2K 1V8 | I2C data for serial camera data support link or differential data lane |
| S3 | GND | PWR/GND | |||||
| S4 | RSVD | X1_ADC_IN4 | SARADC_VIN4 | RSVD | |||
| S5 | CSI0_TX+ / I2C_CAM0_CK | CSI0_I2C_SCL | - | I2C3_SCL_M0 UART3_TX_M0 CAN1_TX_M0 AUDIOPWM_LOUT_N ACODEC_ADC_CLK GPIO1_A1_U |
CSI0 | PU 2.2K 1V8 | I2C clock for serial camera data support link or differential data lane |
| S6 | CAM_MCK | CAM_MCK | AC3 | GMAC1_MDC_M0 PWM14_M0 UART7_TX_M1 PDM_CLK1_M2 VOP_PWM_M1 GPIO3_C4_D |
CSI | 1V8 | Master clock output |
| S7 | CSI0_TX- / I2C_CAM0_DAT | CSI0_I2C_SDA | - | CSI0_I2C_SDA | CSI0 | PU 2.2K 1V8 | I2C data for serial camera data support link or differential data lane |
| S8 | CSI0_CK+ | CSI0_CLKP | AG9 | MIPI_CSI_RX_CLK1P | CSI0 | CSI0 differential clock input (point to point) | |
| S9 | CSI0_CK- | CSI0_CLKN | AH9 | MIPI_CSI_RX_CLK1N | CSI0 | CSI0 differential clock input (point to point) | |
| S10 | GND | PWR/GND | |||||
| S11 | CSI0_RX0+ | CSI0_D0P | AE11 | MIPI_CSI_RX_D2P | CSI0 | CSI0 differential input | |
| S12 | CSI0_RX0- | CSI0_D0N | AD11 | MIPI_CSI_RX_D2N | CSI0 | CSI0 differential input | |
| S13 | GND | PWR/GND | |||||
| S14 | CSI0_RX1+ | CSI0_D1P | AD9 | MIPI_CSI_RX_D3P | CSI0 | CSI0 differential input | |
| S15 | CSI0_RX1- | CSI0_D1N | AE9 | MIPI_CSI_RX_D3N | CSI0 | CSI0 differential input | |
| S16 | GND | PWR/GND | |||||
| S17 | GBE1_MDI0+ | ETH1_TX0P | - | ETH1 | Differential Pair Signals for External Transformer | ||
| S18 | GBE1_MDI0- | ETH1_TX0N | ETH1 | Differential Pair Signals for External Transformer | |||
| S19 | GBE1_LINK100# | ETH1_LINK10/100_ | ETH1 | Link Speed Indication LED for GBE1 100Mbps | |||
| S20 | GBE1_MDI1+ | ETH1_TX1P | ETH1 | Differential Pair Signals for External Transformer | |||
| S21 | GBE1_MDI1- | ETH1_TX1N | ETH1 | Differential Pair Signals for External Transformer | |||
| S22 | GBE1_LINK1000# | ETH1_LINK1000_ | ETH1 | Link Speed Indication LED for GBE1 1000Mbps | |||
| S23 | GBE1_MDI2+ | ETH1_TX2P | ETH1 | Differential Pair Signals for External Transformer | |||
| S24 | GBE1_MDI2- | ETH1_TX2N | ETH1 | Differential Pair Signals for External Transformer | |||
| S25 | GND | PWR/GND | |||||
| S26 | GBE1_MDI3+ | ETH1_TX3P | ETH1 | Differential Pair Signals for External Transformer | |||
| S27 | GBE1_MDI3- | ETH1_TX3N | ETH1 | Differential Pair Signals for External Transformer | |||
| S28 | GBE1_CTREF | +3.3V | ETH1 | Center-Tap Reference Voltage for Carrier Board Ethernet Magnetic (if required by the Module GBE PHY) | |||
| S29 | PCIE_D_TX+ / SERDES_0_TX+ | NC | |||||
| S30 | PCIE_D_TX- / SERDES_0_TX- | NC | |||||
| S31 | GBE1_LINK_ACT# | ETH1_ACT_ | ETH1 | Link / Activity Indication LED Driven Low on Link (10, 100 or 1000 Mbps) Blinks on Activity | |||
| S32 | PCIE_D_RX+ / SERDES_0_RX+ | NC | |||||
| S33 | PCIE_D_RX- / SERDES_0_RX- | NC | |||||
| S34 | GND | PWR/GND | |||||
| S35 | USB4+ | NC | |||||
| S36 | USB4- | NC | |||||
| S37 | USB3_VBUS_DET | NC | |||||
| S38 | AUDIO_MCK | I2S1_MCLK | A19 | I2S1_MCLK_M0 UART3_RTSN_M0 SCR_CLK PCIE30X1_PERSTN_M2 GPIO1_A2_D |
I2S1 | 1V8 | Master Clock Output to I2S Codec(s) |
| S39 | I2S0_LRCK | I2S1_LRCK | A20 | I2S1_LRCK_TX_M0 UART4_RTSN_M0 SCR_RST PCIE30X1_CLKREQN_M2 ACODEC_DAC_SYNC GPIO1_A5_D |
I2S1 | 1V8 | I2S0 Left and Right Synchronization Clock |
| S40 | I2S0_SDOUT | I2S1_SDO | B20 | I2S1_SDO0_M0 UART4_CTSN_M0 SCR_DET AUDIOPWM_ROUT_N ACODEC_DAC_DATAL GPIO1_A7_D |
I2S1 | 1V8 | I2S0 Digital Audio Output |
| S41 | I2S0_SDIN | I2S1_SDI | B21 | I2S1_SDI0_M0 PDM_SDI0_M0 GPIO1_B3_D |
I2S1 | 1V8 | I2S0 Digital Audio Input |
| S42 | I2S0_CK | I2S1_SCLK_PPS | B19 | I2S1_SCLK_TX_M0 UART3_CTSN_M0 SCR_IO PCIE30X1_WAKEN_M2 ACODEC_DAC_CLK GPIO1_A3_D |
I2S1 | 1V8 | I2S0 Digital Audio Clock |
| S43 | ESPI_ALERT0# | ESPI_ALERT0_ | AC2 | GMAC1_MDIO_M0 PWM15_IR_M0 SPDIF_TX_M1 UART7_RX_M1 I2S1_LRCK_RX_M2 GPIO3_C5_D |
eSPI | PU 10K 1V8 | ESPI ALERT0 |
| S44 | ESPI_ALERT1# | ESPI_ALERT1_ | E26 | CLK32K_OUT1 UART8_RX_M0 SPI1_CS1_M0 GPIO2_C6_D |
eSPI | PU 10K 1V8 | ESPI ALERT1 |
| S45 | MDIO_CLK | RGMII0_MDC | H24 | GMAC0_MDC I2S2_LRCK_TX_M0 UART9_RTSN_M0 SPI2_MOSI_M0 GPIO2_C3_D |
RGMII0 | 1V8 | MDIO Signals to Configure Possible PHYs |
| S46 | MDIO_DAT | RGMII0_MDIO | H23 | GMAC0_MDIO I2S2_SDO_M0 UART9_CTSN_M0 SPI2_CS0_M0 GPIO2_C4_D |
RGMII0 | 1V8 | MDIO Signals to Configure Possible PHY |
| S47 | GND | PWR/GND | |||||
| S48 | I2C_GP_CK | I2C4_SCL | E25 | I2C4_SCL_M1 SDMMC1_DET UART8_CTSN_M0 CAN2_TX_M1 GPIO2_B2_U |
I2C4 | PU 10K 1V8 | General Purpose I2C Clock Signal |
| S49 | I2C_GP_DAT | I2C4_SDA | D26 | I2C4_SDA_M1 | I2C4 | PU 10K 1V8 | General Purpose I2C Data Signal |
| S50 | HDA_SYNC / I2S2_LRCK | NC | |||||
| S51 | HDA_SDO / I2S2_SDOUT | NC | |||||
| S52 | HDA_SDI / I2S2_SDIN | NC | |||||
| S53 | HDA_CK / I2S2_CK | NC | |||||
| S54 | SATA_ACT# | SATA2_ACT_ | AH7 | EDP_HPDIN_M0 SPDIF_TX_M2 SATA2_ACT_LED PCIE30X2_PERSTN_M2 I2S3_LRCK_M1 GPIO4_C4_D |
SATA | 3V3 | SATA Activity Indicator |
| S55 | USB5_EN_OC# | NC | |||||
| S56 | ESPI_IO_2 / QSPI_IO_2 | X1_QSPI_D2 | *) | ||||
| S57 | ESPI_IO_3 / QSPI_IO_3 | X1_QSPI_D3 | *) | ||||
| S58 | ESPI_RESET# | ESPI_RESET_ | U3 | CIF_CLKOUT EBC_GDCLK PWM11_IR_M1 GPIO4_C0_D |
eSPI | 1V8 | ESPI Reset |
| S59 | USB5+ | NC | |||||
| S60 | USB5- | NC | |||||
| S61 | GND | PWR/GND | |||||
| S62 | USB3_SSTX+ | USB_OTG_SSTXP | *) | SATA or USB3.0 | USB OTG | USB SS | Transmit Signal Differential Pairs for SuperSpeed |
| S63 | USB3_SSTX- | USB_OTG_SSTXN | *) | SATA or USB3.0 | USB OTG | USB SS | Transmit Signal Differential Pairs for SuperSpeed |
| S64 | GND | PWR/GND | |||||
| S65 | USB3_SSRX+ | USB_OTG_SSRXP | *) | SATA or USB3.0 | USB OTG | USB SS | Receive Signal Differential Pairs for SuperSpeed |
| S66 | USB3_SSRX- | USB_OTG_SSRXN | *) | SATA or USB3.0 | USB OTG | USB SS | Receive Signal Differential Pairs for SuperSpeed |
| S67 | GND | PWR/GND | |||||
| S68 | USB3+ | USB_H3_DP | T2 | USB2_HOST3_DP | USB2 | USB | USB Differential Data Pairs |
| S69 | USB3- | USB_H3_DM | T1 | USB2_HOST3_DM | USB2 | USB | USB Differential Data Pairs |
| S70 | GND | PWR/GND | |||||
| S71 | USB2_SSTX+ | USB_H1_SSTXP | V28 | USB3_HOST1_SSTXP SATA1_TXP QSGMII_TXP_M0 |
USB3 | USB SS | Transmit Signal Differential Pairs for SuperSpeed |
| S72 | USB2_SSTX- | USB_H1_SSTXN | V27 | USB3_HOST1_SSTXN SATA1_TXN QSGMII_TXN_M0 |
USB3 | USB SS | Transmit Signal Differential Pairs for SuperSpeed |
| S73 | GND | PWR/GND | |||||
| S74 | USB2_SSRX+ | USB_H1_SSRXP | U28 | USB3_HOST1_SSRXP SATA1_RXP QSGMII_RXP_M0 |
USB3 | USB SS | Receive Signal Differential Pairs for SuperSpeed |
| S75 | USB2_SSRX- | USB_H1_SSRXN | U27 | USB3_HOST1_SSRXN SATA1_RXN QSGMII_RXN_M0 |
USB3 | USB SS | Receive Signal Differential Pairs for SuperSpeed |
| S76 | PCIE_B_RST# | PCIe1_RST_ | AE23 | PWM4 VOP_PWM_M0 PCIE30X1_PERSTN_M0 MCU_JTAG_TRSTN GPIO0_C3_D |
PCIe1 | 3V3 | PCIe Port B reset output |
| S77 | PCIE_C_RST# | PCIE20_RST_ | AG27 | REFCLK_OUT GPIO0_A0_D |
PCIe2 | 3V3 | PCIe Port C reset output |
| S78 | PCIE_C_RX+ / SERDES_1_RX+ | PCIE20_RXP | Y27 | PCIE20_RXP SATA2_RXP QSGMII_RXP_M1 |
PCIE2 | Differential PCIe link C receive data pair | |
| S79 | PCIE_C_RX- / SERDES_1_RX- | PCIE20_RXN | Y28 | PCIE20_RXN SATA2_RXN QSGMII_RXN_M1 |
PCIE2 | Differential PCIe link C receive data pair | |
| S80 | GND | PWR/GND | |||||
| S81 | PCIE_C_TX+ / SERDES_1_TX+ | PCIE20_TXP | W27 | PCIE20_TXP SATA2_TXP QSGMII_TXP_M1 |
PCIE2 | Differential PCIe link C transmit data pair | |
| S82 | PCIE_C_TX- / SERDES_1_TX- | PCIE20_TXN | W28 | PCIE20_TXN SATA2_TXN QSGMII_TXN_M1 |
PCIE2 | Differential PCIe link C transmit data pair | |
| S83 | GND | PWR/GND | |||||
| S84 | PCIE_B_REFCK+ | PCIe1_CLKP | - | Differential PCIe Link B reference clock output | |||
| S85 | PCIE_B_REFCK- | PCIe1_CLKN | - | Differential PCIe Link B reference clock output | |||
| S86 | GND | PWR/GND | |||||
| S87 | PCIE_B_RX+ | PCIE30_RX1P | AD28 | PCIE30_RX1P | PCIE3 | Differential PCIe link B receive data pair | |
| S88 | PCIE_B_RX- | PCIE30_RX1N | AD27 | PCIE30_RX1N | PCIE3 | Differential PCIe link B receive data pair | |
| S89 | GND | PWR/GND | |||||
| S90 | PCIE_B_TX+ | PCIE30_TX1P | AB28 | PCIE30_TX1P | PCIE3 | Differential PCIe link B transmit data pair | |
| S91 | PCIE_B_TX- | PCIE30_TX1N | AB27 | PCIE30_TX1N | PCIE3 | Differential PCIe link B transmit data pair | |
| S92 | GND | PWR/GND | |||||
| S93 | DP0_LANE0+ | DP_D0P | J28 | EDP_TX_D0P | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S94 | DP0_LANE0- | DP_D0N | K27 | EDP_TX_D0N | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S95 | DP0_AUX_SEL | DP0_AUX_SEL | A21 | I2S1_SDO3_M0 I2S1_SDI1_M0 PDM_SDI1_M0 PCIE20_PERSTN_M2 GPIO1_B2_D |
DP0++ | 1V8 | Auxiliary Selection |
| S96 | DP0_LANE1+ | DP_D1P | K28 | EDP_TX_D1P | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S97 | DP0_LANE1- | DP_D1N | L27 | EDP_TX_D1N | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S98 | DP0_HPD | CPU_DP_HDP | AG23 | PWM3_IR EDP_HPDIN_M1 PCIE30X1_WAKEN_M0 MCU_JTAG_TMS GPIO0_C2_D |
DP0++ | 1V8 | DP Hot Plug Detect Input |
| S99 | DP0_LANE2+ | DP_D2P | L28 | EDP_TX_D2P | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S100 | DP0_LANE2- | DP_D2N | M27 | EDP_TX_D2N | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S101 | GND | PWR/GND | |||||
| S102 | DP0_LANE3+ | DP_D3P | M28 | EDP_TX_D3P | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S103 | DP0_LANE3- | DP_D3N | N27 | EDP_TX_D3N | DP0++ | Primary DP Port Differential Pair Data Lines | |
| S104 | USB3_OTG_ID | NC | |||||
| S105 | DP0_AUX+ | CPU_DP_AUXP | L25 | EDP_TX_AUXP | DP0++ | 3V3 | Primary DP Port Bidirectional Channel used for Link Management and Device Control |
| S106 | DP0_AUX- | CPU_DP_AUXN | M25 | EDP_TX_AUXN | DP0++ | 3V3 | Primary DP Port Bidirectional Channel used for Link Management and Device Control |
| S107 | LCD1_BKLT_EN | LCD1_BKLT_EN | G23 | I2S2_MCLK_M0 ETH0_REFCLKO_25M UART7_RTSN_M0 SPI2_CLK_M0 GPIO2_C1_D |
eDP1 | 1V8 | Secondary LVDS Channel Backlight Enable |
| S108 | LVDS1_CK+ / eDP1_AUX+ / DSI1_CLK+ | DSI1/LVDS_CLKP | AD15 | MIPI_DSI_TX1_CLKP | DSI1 | Secondary DSI Panel Differential Pair Clock Lines | |
| S109 | LVDS1_CK- / eDP1_AUX- / DSI1_CLK- | DSI1/LVDS_CLKN | AE15 | MIPI_DSI_TX1_CLKN | DSI1 | Secondary DSI Panel Differential Pair Clock Lines | |
| S110 | GND | PWR/GND | |||||
| S111 | LVDS1_0+ / eDP1_TX0+ / DSI1_D0+ | DSI1/LVDS_D0P | AD18 | MIPI_DSI_TX1_D0P | DSI1 | Secondary DSI Panel Differential Pair Clock Lines | |
| S112 | LVDS1_0- / eDP1_TX0- / DSI1_D0- | DSI1/LVDS_D0N | AE18 | MIPI_DSI_TX1_D0N | DSI1 | Secondary DSI Panel Differential Pair Clock Lines | |
| S113 | eDP1_HPD / DSI1_TE | DSI1_TE /1M PD | E20 | I2S1_SDO2_M0 I2S1_SDI2_M0 PDM_SDI2_M0 PCIE20_WAKEN_M2 ACODEC_ADC_SYNC GPIO1_B1_D |
DSI1 | 1V8 | Detection of Hot Plug / Unplug of Secondary eDP Display and Notification of the Link Layer |
| S114 | LVDS1_1+ / eDP1_TX1+ / DSI1_D1+ | DSI1/LVDS_D1P | AD17 | MIPI_DSI_TX1_D1P | DSI1 | Secondary DSI Panel Differential Pair Clock Lines | |
| S115 | LVDS1_1- / eDP1_TX1- / DSI1_D1- | DSI1/LVDS_D1N | AC17 | MIPI_DSI_TX1_D1N | DSI1 | Secondary DSI Panel Differential Pair Clock Lines | |
| S116 | LCD1_VDD_EN | LCD_VDD_EN | GPIO4_D2_D | AB9 | DSI1 | 1V8 | Secondary Panel Power Enable |
| S117 | LVDS1_2+ / eDP1_TX2+ / DSI1_D2+ | DSI1/LVDS_D2P | AD14 | MIPI_DSI_TX1_D2P | DSI1 | Secondary DSI Panel Differential Pair Data Lines | |
| S118 | LVDS1_2- / eDP1_TX2- / DSI1_D2- | DSI1/LVDS_D2N | AC14 | MIPI_DSI_TX1_D2N | DSI1 | Secondary DSI Panel Differential Pair Data Lines | |
| S119 | GND | PWR/GND | |||||
| S120 | LVDS1_3+ / eDP1_TX3+ / DSI1_D3+ | DSI1/LVDS_D3P | AD12 | MIPI_DSI_TX1_D3P | DSI1 | Secondary DSI Panel Differential Pair Data Lines | |
| S121 | LVDS1_3- / eDP1_TX3- / DSI1_D3- | DSI1/LVDS_D3N | AE12 | MIPI_DSI_TX1_D3N | DSI1 | Secondary DSI Panel Differential Pair Data Lines | |
| S122 | LCD1_BKLT_PWM | LCD_PWM | AH26 | PWM0_M0 CPUAVS GPIO0_B7_D |
1V8 | DSI1 | Secondary Panel Brightness Control |
| S123 | GPIO13 | GPIO13 | W1 | GMAC1_RXD0_M1 SPI3_CS1_M0 I2S1_LRCK_RX_M1 CAM_CLKOUT0 EBC_SDCE1 GPIO4_A7_D |
GPIO | 1V8 | GPIO Pin 13 Preferred Output |
| S124 | GND | PWR/GND | |||||
| S125 | LVDS0_0+ / eDP0_TX0+ / DSI0_D0+ | DSI0/LVDS_D0P | AH17 | MIPI_DSI_TX0_D0P LVDS_TX0_D0P |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S126 | LVDS0_0- / eDP0_TX0- / DSI0_D0- | DSI0/LVDS_D0N | AG17 | MIPI_DSI_TX0_D0N LVDS_TX0_D0N |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S127 | LCD0_BKLT_EN | LCD0_BKLT_EN | AH6 | HDMITX_CEC_M0 SPI3_CS1_M1 GPIO4_D1_U |
DSI0 | 1V8 | Primary Panel Backlight Enable |
| S128 | LVDS0_1+ / eDP0_TX1+ / DSI0_D1+ | DSI0/LVDS_D1P | AH16 | MIPI_DSI_TX0_D1P LVDS_TX0_D1P |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S129 | LVDS0_1- / eDP0_TX1- / DSI0_D1- | DSI0/LVDS_D1N | AG16 | MIPI_DSI_TX0_D1N LVDS_TX0_D1N |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S130 | GND | PWR/GND | |||||
| S131 | LVDS0_2+ / eDP0_TX2+ / DSI0_D2+ | DSI0/LVDS_D2P | AH14 | MIPI_DSI_TX0_D2P LVDS_TX0_D2P |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S132 | LVDS0_2- / eDP0_TX2- / DSI0_D2- | DSI0/LVDS_D2N | AG14 | MIPI_DSI_TX0_D2N LVDS_TX0_D2N |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S133 | LCD0_VDD_EN | LCD_VDD_EN | AB9 | GPIO4_D2_D | DSI0 | 1V8 | Primary Panel Power Enable |
| S134 | LVDS0_CK+ / eDP0_AUX+ / DSI0_CLK+ | DSI0/LVDS_CLKP | AH15 | MIPI_DSI_TX0_CLKP LVDS_TX0_CLKP |
DSI0 | Primary DSI Panel Differential Pair Clock Lines | |
| S135 | LVDS0_CK- / eDP0_AUX- / DSI0_CLK- | DSI0/LVDS_CLKN | AG15 | MIPI_DSI_TX0_CLKN LVDS_TX0_CLKN |
DSI0 | Primary DSI Panel Differential Pair Clock Lines | |
| S136 | GND | PWR/GND | |||||
| S137 | LVDS0_3+ / eDP0_TX3+ / DSI0_D3+ | DSI0/LVDS_D3P | AH13 | MIPI_DSI_TX0_D3P LVDS_TX0_D3P |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S138 | LVDS0_3- / eDP0_TX3- / DSI0_D3- | DSI0/LVDS_D3N | AG13 | MIPI_DSI_TX0_D3N LVDS_TX0_D3N |
DSI0 | Primary DSI Panel Differential Pair Data Lines | |
| S139 | I2C_LCD_CK | I2C1_SCL | AG24 | I2C1_SCL CAN0_TX_M0 PCIE30X1_BUTTONRSTN MCU_JTAG_TDO GPIO0_B3_U |
DSI | PU 2.2K 1V8 | I2C clock to read LCD display EDID EEPROMs |
| S140 | I2C_LCD_DAT | I2C1_SDA | AB20 | I2C1_SDA CAN0_RX_M0 PCIE20_BUTTONRSTN MCU_JTAG_TCK GPIO0_B4_U |
DSI | PU 2.2K 1V8 | DDC Data Line Used for Flat Panel Detection and Control |
| S141 | LCD0_BKLT_PWM | LCD_PWM | AH26 | PWM0_M0 CPUAVS GPIO0_B7_D |
DSI0 | 1V8 | Primary Panel Brightness Control |
| S142 | GPIO12 | GPIO12 | AD25 | GPIO0_D5_D | GPIO | 1V8 | GPIO Pin 12 Preferred Output |
| S143 | GND | PWR/GND | |||||
| S144 | eDP0_HPD / DSI0_TE | DSI0_TE /1M PD | D20 | I2S1_SDO1_M0 I2S1_SDI3_M0 PDM_SDI3_M0 PCIE20_CLKREQN_M2 ACODEC_DAC_DATAR GPIO1_B0_D |
DSI0 | 1V8 | Primary DSI Panel Tearing Effect Signal |
| S145 | WDT_TIME_OUT# | X1_WDT_TIME_OUT_ | - | WATCHDOG | 1V8 | Watch-Dog-Timer Output, low active | |
| S146 | PCIE_WAKE# | PCIe_WAKE_ | AC21 | PWM6 SPI0_MISO_M0 PCIE30X2_WAKEN_M0 GPIO0_C5_D |
PCIE | 3V3 | PCIe wake up interrupt to host – common to PCIe links A, B, C, D |
| S147 | VDD_RTC | VDD_RTC | PWR RTC | ||||
| S148 | LID# | X1_LID_ | - | MANAGEMENT | PU 1.8K 1V8 | Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in inactive state. Active low, level sensitive. Should be de-bounced on the Module. | |
| S149 | SLEEP# | X1_SLEEP_ | - | MANAGEMENT | PU 1.8K 1V8 | Sleep indicator from Carrier Board. May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module. | |
| S150 | VIN_PWR_BAD# | X1_VIN_PWR_BAD_ | - | MANAGEMENT | PU 10K 5V | Power bad indication from Carrier Board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall not be enabled while this signal is held low by the Carrier. | |
| S151 | CHARGING# | NC | MANAGEMENT | Held low by Carrier during battery charging. Carrier to float the line when charge is complete. | |||
| S152 | CHARGER_PRSNT# | NC | MANAGEMENT | Held low by Carrier if DC input for battery charger is present | |||
| S153 | CARRIER_STBY# | X1_CARRIER_STBY_ | - | MANAGEMENT | 1V8 | The Module shall drive this signal low when the system is in a standby power state. | |
| S154 | CARRIER_PWR_ON | X1_CARRIER_PWR_ON | - | MANAGEMENT | 1V8 | Carrier Board circuits (apart from power management and power path circuits) should not be powered up until the Module asserts the CARRIER_PWR_ON signal. | |
| S155 | FORCE_RECOV# | RECOVERY_ | BOOT | PU 10K 1V8 | Low on this pin allows nonprotected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode – such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier. | ||
| S156 | BATLOW# | X1_BATLOW_ | - | MANAGEMENT | Battery low indication to Module. Carrier to float the line in inactive state | ||
| S157 | TEST# | X1_ADC_IN2 | - | MANAGEMENT | Held Low by Carrier to Invoke Module Vendor Specific Test Functions | ||
| S158 | GND | PWR/GND |